soc/amd/cezanne/acpi: Add MMIO devices
The devices were copied from picasso with the following modifications:
* UART{2,3} were deleted
* I2C{0,1} were added
* eMMC was removed since it hasn't been validated
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Iddfb975e9292785d0951dd7bb31c1997d2185abd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Raul E Rangel
Patrick Georgi
parent
1156acbb7e
commit
980721b3ed
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@ -0,0 +1,287 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <soc/amd/common/acpi/aoac.asl>
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#include <soc/gpio.h>
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#include <soc/iomap.h>
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#include <amdblocks/acpimmio_map.h>
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Device (AAHB)
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{
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Name (_HID, "AAHB0000")
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Name (_UID, 0x0)
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Name (_CRS, ResourceTemplate()
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{
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Memory32Fixed (ReadWrite, ALINK_AHB_ADDRESS, 0x2000)
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})
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Method (_STA, 0x0, NotSerialized)
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{
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Return (0x0F)
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}
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}
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Device (GPIO)
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{
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Name (_HID, GPIO_DEVICE_NAME)
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Name (_CID, GPIO_DEVICE_NAME)
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Name (_UID, 0)
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Name (_DDN, GPIO_DEVICE_DESC)
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Method (_CRS, 0) {
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Local0 = ResourceTemplate() {
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Interrupt (
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ResourceConsumer,
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Level,
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ActiveLow,
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Exclusive, , , IRQR)
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{ 0 }
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Memory32Fixed (ReadWrite, ACPIMMIO_GPIO0_BASE, 0x400)
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}
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CreateDWordField (Local0, IRQR._INT, IRQN)
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If (PICM) {
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IRQN = IGPI
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} Else {
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IRQN = PGPI
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}
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If (IRQN == 0x1f) {
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Return (ResourceTemplate() {
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Memory32Fixed (ReadWrite, ACPIMMIO_GPIO0_BASE, 0x400)
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})
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} Else {
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Return (Local0)
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}
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}
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Method (_STA, 0x0, NotSerialized)
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{
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Return (0x0F)
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}
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}
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Device (FUR0)
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{
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Name (_HID, "AMDI0020")
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Name (_UID, 0x0)
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Method (_CRS, 0) {
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Local0 = ResourceTemplate() {
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Interrupt (
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ResourceConsumer,
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Edge,
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ActiveHigh,
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Exclusive, , , IRQR)
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{ 0 }
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Memory32Fixed (ReadWrite, APU_UART0_BASE, 0x1000)
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}
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CreateDWordField (Local0, IRQR._INT, IRQN)
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If (PICM) {
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IRQN = IUA0
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} Else {
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IRQN = PUA0
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}
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If (IRQN == 0x1f) {
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Return (ResourceTemplate() {
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Memory32Fixed (ReadWrite, APU_UART0_BASE, 0x1000)
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})
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} Else {
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Return (Local0)
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}
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}
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AOAC_DEVICE(11, 0)
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}
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Device (FUR1) {
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Name (_HID, "AMDI0020")
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Name (_UID, 0x1)
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Method (_CRS, 0) {
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Local0 = ResourceTemplate() {
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Interrupt (
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ResourceConsumer,
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Edge,
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ActiveHigh,
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Exclusive, , , IRQR)
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{ 0 }
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Memory32Fixed (ReadWrite, APU_UART1_BASE, 0x1000)
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}
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CreateDWordField (Local0, IRQR._INT, IRQN)
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If (PICM) {
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IRQN = IUA1
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} Else {
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IRQN = PUA1
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}
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If (IRQN == 0x1f) {
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Return (ResourceTemplate() {
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Memory32Fixed (ReadWrite, APU_UART1_BASE, 0x1000)
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})
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} Else {
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Return (Local0)
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}
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}
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AOAC_DEVICE(12, 0)
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}
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Device (I2C0) {
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Name (_HID, "AMDI0010")
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Name (_UID, 0x0)
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Method (_CRS, 0) {
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Local0 = ResourceTemplate() {
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Interrupt (
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ResourceConsumer,
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Edge,
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ActiveHigh,
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Exclusive, , , IRQR)
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{ 0 }
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Memory32Fixed (ReadWrite, APU_I2C0_BASE, 0x1000)
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}
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CreateDWordField (Local0, IRQR._INT, IRQN)
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If (PICM) {
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IRQN = II20
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} Else {
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IRQN = PI20
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}
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If (IRQN == 0x1f) {
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Return (ResourceTemplate() {
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Memory32Fixed (ReadWrite, APU_I2C0_BASE, 0x1000)
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})
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} Else {
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Return (Local0)
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}
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}
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Method (_STA, 0x0, NotSerialized)
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{
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Return (0x0F)
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}
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AOAC_DEVICE(5, 0)
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}
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Device (I2C1) {
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Name (_HID, "AMDI0010")
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Name (_UID, 0x1)
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Method (_CRS, 0) {
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Local0 = ResourceTemplate() {
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Interrupt (
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ResourceConsumer,
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Edge,
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ActiveHigh,
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Exclusive, , , IRQR)
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{ 0 }
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Memory32Fixed (ReadWrite, APU_I2C1_BASE, 0x1000)
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}
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CreateDWordField (Local0, IRQR._INT, IRQN)
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If (PICM) {
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IRQN = II21
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} Else {
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IRQN = PI21
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}
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If (IRQN == 0x1f) {
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Return (ResourceTemplate() {
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Memory32Fixed (ReadWrite, APU_I2C1_BASE, 0x1000)
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})
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} Else {
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Return (Local0)
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}
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}
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Method (_STA, 0x0, NotSerialized)
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{
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Return (0x0F)
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}
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AOAC_DEVICE(6, 0)
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}
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Device (I2C2) {
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Name (_HID, "AMDI0010")
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Name (_UID, 0x2)
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Method (_CRS, 0) {
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Local0 = ResourceTemplate() {
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Interrupt (
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ResourceConsumer,
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Edge,
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ActiveHigh,
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Exclusive, , , IRQR)
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{ 0 }
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Memory32Fixed (ReadWrite, APU_I2C2_BASE, 0x1000)
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}
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CreateDWordField (Local0, IRQR._INT, IRQN)
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If (PICM) {
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IRQN = II22
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} Else {
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IRQN = PI22
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}
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If (IRQN == 0x1f) {
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Return (ResourceTemplate() {
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Memory32Fixed (ReadWrite, APU_I2C2_BASE, 0x1000)
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})
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} Else {
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Return (Local0)
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}
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}
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Method (_STA, 0x0, NotSerialized)
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{
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Return (0x0F)
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}
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AOAC_DEVICE(7, 0)
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}
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Device (I2C3)
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{
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Name (_HID, "AMDI0010")
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Name (_UID, 0x3)
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Method (_CRS, 0) {
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Local0 = ResourceTemplate() {
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Interrupt (
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ResourceConsumer,
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Edge,
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ActiveHigh,
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Exclusive, , , IRQR)
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{ 0 }
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Memory32Fixed (ReadWrite, APU_I2C3_BASE, 0x1000)
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}
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CreateDWordField (Local0, IRQR._INT, IRQN)
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If (PICM) {
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IRQN = II23
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} Else {
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IRQN = PI23
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}
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If (IRQN == 0x1f) {
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Return (ResourceTemplate() {
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Memory32Fixed (ReadWrite, APU_I2C3_BASE, 0x1000)
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})
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} Else {
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Return (Local0)
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}
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}
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Method (_STA, 0x0, NotSerialized)
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{
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Return (0x0F)
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}
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AOAC_DEVICE(8, 0)
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}
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Device (MISC)
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{
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Name (_HID, "AMD0040")
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Name (_UID, 0x3)
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Name (_CRS, ResourceTemplate() {
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Memory32Fixed (ReadWrite, ACPIMMIO_MISC_BASE, 0x100)
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})
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Name (_DSD, Package ()
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{
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ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
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Package ()
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{
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Package () { "is-rv", 1 },
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},
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})
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Method (_STA, 0x0, NotSerialized)
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{
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Return (0x0F)
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}
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}
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@ -0,0 +1,65 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* PCI IRQ mapping registers, C00h-C01h. */
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OperationRegion(PRQM, SystemIO, 0x00000c00, 0x00000002)
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Field(PRQM, ByteAcc, NoLock, Preserve) {
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PRQI, 0x00000008,
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PRQD, 0x00000008, /* Offset: 1h */
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}
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/*
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* All PIC indexes are prefixed with P.
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* All IO-APIC indexes are prefixed with I.
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*/
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IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
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PIRA, 0x00000008, /* Index 0: INTA */
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PIRB, 0x00000008, /* Index 1: INTB */
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PIRC, 0x00000008, /* Index 2: INTC */
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PIRD, 0x00000008, /* Index 3: INTD */
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PIRE, 0x00000008, /* Index 4: INTE */
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PIRF, 0x00000008, /* Index 5: INTF */
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PIRG, 0x00000008, /* Index 6: INTG */
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PIRH, 0x00000008, /* Index 7: INTH */
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Offset (0x43),
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PMMC, 0x00000008, /* Index 0x43: eMMC */
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Offset (0x62),
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PGPI, 0x00000008, /* Index 0x62: GPIO */
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Offset (0x70),
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PI20, 0x00000008, /* Index 0x70: I2C0 */
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PI21, 0x00000008, /* Index 0x71: I2C1 */
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PI22, 0x00000008, /* Index 0x72: I2C2 */
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PI23, 0x00000008, /* Index 0x73: I2C3 */
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PUA0, 0x00000008, /* Index 0x74: UART0 */
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PUA1, 0x00000008, /* Index 0x75: UART1 */
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PI24, 0x00000008, /* Index 0x76: I2C4 */
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PI25, 0x00000008, /* Index 0x77: I2C5 */
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/* IO-APIC IRQs */
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Offset (0x80),
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IORA, 0x00000008, /* Index 0x80: INTA */
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IORB, 0x00000008, /* Index 0x81: INTB */
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IORC, 0x00000008, /* Index 0x82: INTC */
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IORD, 0x00000008, /* Index 0x83: INTD */
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IORE, 0x00000008, /* Index 0x84: INTE */
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IORF, 0x00000008, /* Index 0x85: INTF */
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IORG, 0x00000008, /* Index 0x86: INTG */
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IORH, 0x00000008, /* Index 0x87: INTH */
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Offset (0xC3),
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IMMC, 0x00000008, /* Index 0xC3: eMMC */
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Offset (0xE2),
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IGPI, 0x00000008, /* Index 0xE2: GPIO */
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Offset (0xF0),
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II20, 0x00000008, /* Index 0xF0: I2C0 */
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II21, 0x00000008, /* Index 0xF1: I2C1 */
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II22, 0x00000008, /* Index 0xF2: I2C2 */
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II23, 0x00000008, /* Index 0xF3: I2C3 */
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IUA0, 0x00000008, /* Index 0xF4: UART0 */
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IUA1, 0x00000008, /* Index 0xF5: UART1 */
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II24, 0x00000008, /* Index 0xF6: I2C4 */
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II25, 0x00000008, /* Index 0xF7: I2C5 */
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}
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@ -5,4 +5,8 @@ Scope(\_SB) {
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#include <arch/x86/acpi/globutil.asl>
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#include <soc/amd/common/acpi/gpio_bank_lib.asl>
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#include "pci_int_defs.asl"
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#include "mmio.asl"
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} /* End \_SB scope */
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@ -3,6 +3,8 @@
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#ifndef AMD_CEZANNE_IOMAP_H
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#define AMD_CEZANNE_IOMAP_H
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#if ENV_X86
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/* MMIO Ranges */
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#define SPI_BASE_ADDRESS 0xfec10000
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@ -14,6 +16,11 @@
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/* FCH AL2AHB Registers */
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#define ALINK_AHB_ADDRESS 0xfedc0000
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#define APU_I2C0_BASE 0xfedc2000
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#define APU_I2C1_BASE 0xfedc3000
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#define APU_I2C2_BASE 0xfedc4000
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#define APU_I2C3_BASE 0xfedc5000
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#define APU_DMAC0_BASE 0xfedc7000
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#define APU_DMAC1_BASE 0xfedc8000
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#define APU_UART0_BASE 0xfedc9000
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@ -21,6 +28,8 @@
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#define FLASH_BASE_ADDR ((0xffffffff - CONFIG_ROM_SIZE) + 1)
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#endif /* ENV_X86 */
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/* I/O Ranges */
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#define NCP_ERR 0x00f0
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#define ACPI_IO_BASE 0x0400
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