emulation/qemu-power8: initial mainboard and arch commit

This builds and produces an image.

The next step is to get a 'halt' instruction into the boot block and then attach with qemu.

I can't get the powerpc64le-linux-gnu-ld.bfd to recognize any output arch but
powerpc. That makes no sense to me.

Change-Id: Ia2a5fe07a1457e7b6974ab1473539c7447d7a449
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/13704
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Ronald G. Minnich 2016-02-12 22:37:48 +00:00 committed by Martin Roth
parent 41462bd0c3
commit 9831244cb8
31 changed files with 1018 additions and 0 deletions

25
src/arch/power8/Kconfig Normal file
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config ARCH_POWER8
bool
default n
config ARCH_BOOTBLOCK_POWER8
bool
default n
select ARCH_POWER8
select BOOTBLOCK_CUSTOM
select C_ENVIRONMENT_BOOTBLOCK
select ARCH_VERSTAGE_POWER8
select ARCH_ROMSTAGE_POWER8
select ARCH_RAMSTAGE_POWER8
config ARCH_VERSTAGE_POWER8
bool
default n
config ARCH_ROMSTAGE_POWER8
bool
default n
config ARCH_RAMSTAGE_POWER8
bool
default n

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################################################################################
##
## This file is part of the coreboot project.
##
## Copyright (C) 2014 The ChromiumOS Authors
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
################################################################################
power8_flags = -I$(src)/arch/power8/
power8_asm_flags =
################################################################################
## bootblock
################################################################################
ifeq ($(CONFIG_ARCH_BOOTBLOCK_POWER8),y)
bootblock-y = bootblock.S stages.c
bootblock-y += boot.c
bootblock-y += rom_media.c
bootblock-y += \
$(top)/src/lib/memchr.c \
$(top)/src/lib/memcmp.c \
$(top)/src/lib/memcpy.c \
$(top)/src/lib/memmove.c \
$(top)/src/lib/memset.c
$(objcbfs)/bootblock.debug: $$(bootblock-objs)
@printf " LINK $(subst $(obj)/,,$(@))\n"
$(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) \
-T $(call src-to-obj,bootblock,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) \
$(LIBGCC_FILE_NAME_bootblock) --end-group $(COMPILER_RT_bootblock)
endif
################################################################################
## romstage
################################################################################
ifeq ($(CONFIG_ARCH_ROMSTAGE_POWER8),y)
romstage-y += boot.c
romstage-y += stages.c
romstage-y += rom_media.c
romstage-y += \
$(top)/src/lib/memchr.c \
$(top)/src/lib/memcmp.c \
$(top)/src/lib/memcpy.c \
$(top)/src/lib/memmove.c \
$(top)/src/lib/memset.c
romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
# Build the romstage
$(objcbfs)/romstage.debug: $$(romstage-objs)
@printf " LINK $(subst $(obj)/,,$(@))\n"
$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) -T $(call src-to-obj,romstage,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group $(COMPILER_RT_romstage)
romstage-c-ccopts += $(power8_flags)
romstage-S-ccopts += $(power8_asm_flags)
CBFSTOOL_PRE1_OPTS = -v -m power8 -s $(CONFIG_CBFS_SIZE)
endif
################################################################################
## ramstage
################################################################################
ifeq ($(CONFIG_ARCH_RAMSTAGE_POWER8),y)
ramstage-y += rom_media.c
ramstage-y += stages.c
ramstage-y += misc.c
ramstage-y += boot.c
ramstage-y += tables.c
ramstage-y += \
$(top)/src/lib/memchr.c \
$(top)/src/lib/memcmp.c \
$(top)/src/lib/memcpy.c \
$(top)/src/lib/memmove.c \
$(top)/src/lib/memset.c
$(eval $(call create_class_compiler,rmodules,power8))
ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/mainboard.c
# Build the ramstage
$(objcbfs)/ramstage.debug: $$(ramstage-objs)
@printf " CC $(subst $(obj)/,,$(@))\n"
$(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) -T $(call src-to-obj,ramstage,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group $(COMPILER_RT_ramstage)
ramstage-c-ccopts += $(power8_flags)
ramstage-S-ccopts += $(power8_asm_flags)
endif

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src/arch/power8/boot.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright 2013 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <program_loading.h>
void arch_prog_run(struct prog *prog)
{
void (*doit)(void *) = prog_entry(prog);
doit(prog_entry_arg(prog));
}

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/*
* Early initialization code for power8.
*
* Copyright 2013 Google Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
* GNU General Public License for more details.
*/
.section ".text._start", "ax", %progbits
.globl _start
_start:
b _start
.section ".id", "a", %progbits
.section ".id", "a", @progbits
.globl __id_start
__id_start:
ver:
.asciz "4" //COREBOOT_VERSION
vendor:
.asciz "qemu" //CONFIG_MAINBOARD_VENDOR
part:
.asciz "1" //CONFIG_MAINBOARD_PART_NUMBER
/* Reverse offset to the vendor id */
.long __id_end + CONFIG_ID_SECTION_OFFSET - ver
/* Reverse offset to the vendor id */
.long __id_end + CONFIG_ID_SECTION_OFFSET - vendor
/* Reverse offset to the part number */
.long __id_end + CONFIG_ID_SECTION_OFFSET - part
/* of this romimage */
.long CONFIG_ROM_SIZE
.globl __id_end
__id_end:
.previous

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src/arch/power8/id.ld Normal file
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/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
SECTIONS {
. = (0xffffffff - CONFIG_ID_SECTION_OFFSET) - (__id_end - __id_start) + 1;
.id (.): {
*(.id)
}
}

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/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _BYTEORDER_H
#define _BYTEORDER_H
#define __LITTLE_ENDIAN 1234
#endif /* _BYTEORDER_H */

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/*
* This file is part of the coreboot project.
*
* Copyright 2012 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __ARCH_CPU_H__
#define __ARCH_CPU_H__
#define asmlinkage
#if !defined(__PRE_RAM__)
#include <device/device.h>
struct cpu_driver {
struct device_operations *ops;
struct cpu_device_id *id_table;
};
struct thread;
struct cpu_info {
device_t cpu;
unsigned long index;
#if CONFIG_COOP_MULTITASKING
struct thread *thread;
#endif
};
struct cpuinfo_power8 {
uint8_t power8; /* CPU family */
uint8_t power8_vendor; /* CPU vendor */
uint8_t power8_model;
};
#endif
struct cpu_info *cpu_info(void);
#endif /* __ARCH_CPU_H__ */

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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef ARCH_EARLY_VARIABLES_H
#define ARCH_EARLY_VARIABLES_H
#define CAR_GLOBAL
#define CAR_MIGRATE(migrate_fn_)
static inline void *car_get_var_ptr(void *var) { return var; }
#define car_get_var(var) (var)
#define car_sync_var(var) (var)
#define car_set_var(var, val) do { (var) = (val); } while (0)
#endif

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/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _ARCH_EXCEPTION_H
#define _ARCH_EXCEPTION_H
static inline void exception_init(void)
{
}
#endif

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/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* We use ELF as output format. So that we can debug the code in some form. */
OUTPUT_ARCH(powerpc)
PHDRS
{
to_load PT_LOAD;
}
#ifdef __BOOTBLOCK__
ENTRY(_start)
#else
ENTRY(stage_entry)
#endif

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/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
static inline __attribute__ ((always_inline)) void hlt(void)
{
while (1)
;
}

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/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _ASM_IO_H
#define _ASM_IO_H
#include <stdint.h>
static inline void outb(uint8_t value, uint16_t port)
{
}
static inline void outw(uint16_t value, uint16_t port)
{
}
static inline void outl(uint32_t value, uint16_t port)
{
}
static inline uint8_t inb(uint16_t port)
{
return 0;
}
static inline uint16_t inw(uint16_t port)
{
return 0;
}
static inline uint32_t inl(uint16_t port)
{
return 0;
}
#endif

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/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* This file contains macro definitions for memlayout.ld linker scripts. */
#ifndef __ARCH_MEMLAYOUT_H
#define __ARCH_MEMLAYOUT_H
/* TODO: Double-check that that's the correct alignment for our ABI. */
#define STACK(addr, size) REGION(stack, addr, size, 8)
/* TODO: Need to add DMA_COHERENT region like on ARM? */
#endif /* __ARCH_MEMLAYOUT_H */

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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 The ChromiumOS Authors
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __ARCH_STAGES_H
#define __ARCH_STAGES_H
#include <main_decl.h>
void stage_entry(void) __attribute__((section(".text.stage_entry")));
#endif

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/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef POWER8_STDINT_H
#define POWER8_STDINT_H
/* Exact integral types */
typedef unsigned char uint8_t;
typedef signed char int8_t;
typedef unsigned short uint16_t;
typedef signed short int16_t;
typedef unsigned int uint32_t;
typedef signed int int32_t;
typedef unsigned long long uint64_t;
typedef signed long long int64_t;
/* Small types */
typedef unsigned char uint_least8_t;
typedef signed char int_least8_t;
typedef unsigned short uint_least16_t;
typedef signed short int_least16_t;
typedef unsigned int uint_least32_t;
typedef signed int int_least32_t;
typedef unsigned long long uint_least64_t;
typedef signed long long int_least64_t;
/* Fast Types */
typedef unsigned char uint_fast8_t;
typedef signed char int_fast8_t;
typedef unsigned int uint_fast16_t;
typedef signed int int_fast16_t;
typedef unsigned int uint_fast32_t;
typedef signed int int_fast32_t;
typedef unsigned long long uint_fast64_t;
typedef signed long long int_fast64_t;
typedef long long int intmax_t;
typedef unsigned long long uintmax_t;
typedef uint8_t u8;
typedef uint16_t u16;
typedef uint32_t u32;
typedef uint64_t u64;
typedef int8_t s8;
typedef int16_t s16;
typedef int32_t s32;
typedef int64_t s64;
typedef uint8_t bool;
#define true 1
#define false 0
/* Types for `void *' pointers. */
typedef s64 intptr_t;
typedef u64 uintptr_t;
#endif /* POWER8_STDINT_H */

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src/arch/power8/misc.c Normal file
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/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <delay.h>
void init_timer(void)
{
}
void udelay(unsigned int n)
{
}

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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2002 Eric Biederman
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
.section ".rom.data", "a", @progbits
.section ".rom.text", "ax", @progbits

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/*
* This file is part of the coreboot project.
*
* Copyright 2015 Google Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <boot_device.h>
/* This assumes that the CBFS resides at 0x0, which is true for the default
* configuration. */
static const struct mem_region_device boot_dev =
MEM_REGION_DEV_INIT(NULL, CONFIG_ROM_SIZE);
const struct region_device *boot_device_ro(void)
{
return &boot_dev.rdev;
}

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src/arch/power8/stages.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/*
* This file contains entry/exit functions for each stage during coreboot
* execution (bootblock entry and ramstage exit will depend on external
* loading).
*
* Entry points must be placed at the location the previous stage jumps
* to (the lowest address in the stage image). This is done by giving
* stage_entry() its own section in .text and placing it first in the
* linker script.
*/
#include <arch/stages.h>
void stage_entry(void)
{
main();
}

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src/arch/power8/tables.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2003 Eric Biederman
* Copyright (C) 2005 Steve Magnani
* Copyright (C) 2008-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <console/console.h>
#include <cpu/cpu.h>
#include <boot/tables.h>
#include <boot/coreboot_tables.h>
#include <string.h>
#include <cbmem.h>
#include <lib.h>
#define MAX_COREBOOT_TABLE_SIZE (8 * 1024)
// WTF. this does not agree with the prototype!
static struct lb_memory *wtf_write_tables(void)
{
unsigned long table_pointer, new_table_pointer;
post_code(0x9d);
table_pointer = (unsigned long)cbmem_add(CBMEM_ID_CBTABLE,
MAX_COREBOOT_TABLE_SIZE);
if (!table_pointer) {
printk(BIOS_ERR, "Could not add CBMEM for coreboot table.\n");
return NULL;
}
new_table_pointer = write_coreboot_table(0UL, 0UL,
table_pointer, table_pointer);
if (new_table_pointer > (table_pointer + MAX_COREBOOT_TABLE_SIZE)) {
printk(BIOS_ERR, "coreboot table didn't fit (%lx/%x bytes)\n",
new_table_pointer - table_pointer,
MAX_COREBOOT_TABLE_SIZE);
}
printk(BIOS_DEBUG, "coreboot table: %ld bytes.\n",
new_table_pointer - table_pointer);
post_code(0x9e);
/* Print CBMEM sections */
cbmem_list();
// return get_lb_mem();
return NULL;
}
void lb_arch_add_records(struct lb_header *header)
{
}
void write_tables(void)
{
wtf_write_tables();
}

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##
## This file is part of the coreboot project.
##
## Copyright (C) 2014 Google Inc.
##
## This software is licensed under the terms of the GNU General Public
## License version 2, as published by the Free Software Foundation, and
## may be copied, distributed, and modified under those terms.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
# To execute, do:
# qemu-system-??
if BOARD_EMULATION_QEMU_POWER8
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select BOARD_ROMSIZE_KB_4096
select ARCH_BOOTBLOCK_POWER8
select HAVE_UART_SPECIAL
select ARCH_POWER8
config MAINBOARD_DIR
string
default "emulation/qemu-power8"
config MAINBOARD_PART_NUMBER
string
default "QEMU POWER8"
config MAX_CPUS
int
default 1
config MAINBOARD_VENDOR
string
default "QEMU"
config DRAM_SIZE_MB
int
default 32768
# Memory map for qemu power8
config RAMTOP
hex
default 0x1000000
endif # BOARD_EMULATION_QEMU_POWER8

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config BOARD_EMULATION_QEMU_POWER8
bool "QEMU power8"

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##
## This file is part of the coreboot project.
##
## Copyright (C) 2013 Google Inc.
##
## This software is licensed under the terms of the GNU General Public
## License version 2, as published by the Free Software Foundation, and
## may be copied, distributed, and modified under those terms.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
bootblock-y += bootblock.c
bootblock-y += uart.c
romstage-y += cbmem.c
ramstage-y += cbmem.c
romstage-y += romstage.c
romstage-y += uart.c
ramstage-y += uart.c
bootblock-y += memlayout.ld
romstage-y += memlayout.ld
ramstage-y += memlayout.ld

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Board name: QEMU POWER8
Category: emulation

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/*
* This file is part of the coreboot project.
*
* Copyright 2013 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <bootblock_common.h>
#include <console/console.h>
#include <program_loading.h>
// the qemu part of all this is very, very non-hardware like.
// so it gets its own bootblock.
void main(void)
{
if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) {
console_init();
}
run_romstage();
}

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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <cbmem.h>
void *cbmem_top(void)
{
/* Top of cbmem is at lowest usable DRAM address below 4GiB. */
/* For now, last 1M of 4G */
void *ptr = (void *) ((1ULL << 32) - 1048576);
return ptr;
}

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##
## This file is part of the coreboot project.
##
## Copyright (C) 2014 Google, Inc.
##
## This software is licensed under the terms of the GNU General Public
## License version 2, as published by the Free Software Foundation, and
## may be copied, distributed, and modified under those terms.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
chip cpu/qemu-power8
device cpu_cluster 0 on end
end

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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <console/console.h>
#include <device/device.h>
#include <cbmem.h>
static void mainboard_enable(device_t dev)
{
if (!dev) {
printk(BIOS_EMERG, "No dev0; die\n");
while (1)
;
}
// Where does ram live?
ram_resource(dev, 0, 2048, 32768);
cbmem_recovery(0);
}
struct chip_operations mainboard_ops = {
.enable_dev = mainboard_enable,
};

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/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <memlayout.h>
#include <arch/header.ld>
// TODO: fill in these blanks for Power8.
SECTIONS
{
DRAM_START(0x0)
BOOTBLOCK(0x0, 64K)
ROMSTAGE(0x20000, 128K)
STACK(0x40000, 0x3ff00)
PRERAM_CBMEM_CONSOLE(0x80000, 8K)
RAMSTAGE(0x100000, 16M)
}

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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <console/console.h>
#include <program_loading.h>
void main(void)
{
console_init();
run_ramstage();
}

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/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <types.h>
#include <console/uart.h>
#include <arch/io.h>
#include <boot/coreboot_tables.h>
static uint8_t *buf = (void *)0;
uintptr_t uart_platform_base(int idx)
{
return (uintptr_t) buf;
}
void uart_init(int idx)
{
}
unsigned char uart_rx_byte(int idx)
{
return 0;
}
void uart_tx_byte(int idx, unsigned char data)
{
}
void uart_tx_flush(int idx)
{
}
#ifndef __PRE_RAM__
void uart_fill_lb(void *data)
{
struct lb_serial serial;
serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;
serial.baseaddr = 0;
serial.baud = 115200;
serial.regwidth = 1;
lb_add_serial(&serial, data);
lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data);
}
#endif