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mb/google/puff: Update DPTF parameters for kaisa and duffy 

1. Apply the DPTF parameters receive from the thermal team.
2. Change PL2 min value from 25W to 15W.
3. Change PL2 max value from 64W to 51W.

BUG=b:166696500
BRANCH=puff
TEST=build and verify by thermal team

Change-Id: I53a4e8809369883c3ba77744fdc05fb510408209
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44903
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
David Wu 2020-08-28 17:26:36 +08:00 committed by Edward O'Callaghan
parent 8e6d5f2937
commit 98369131d7
2 changed files with 38 additions and 32 deletions
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35
src/mainboard/google/hatch/variants/duffy/overridetree.cb
View File

@ -1,6 +1,11 @@
chip soc/intel/cannonlake
register "tcc_offset" = "5" # TCC of 95C
register "power_limits_config" = "{
.tdp_pl1_override = 15,
.tdp_pl2_override = 51,
}"
# Auto-switch between X4 NVMe and X2 NVMe.
register "TetonGlacierMode" = "1"
@ -271,29 +276,27 @@ chip soc/intel/cannonlake
chip drivers/intel/dptf
## Active Policy
register "policies.active[0]" = "{.target=DPTF_CPU,
.thresholds={TEMP_PCT(90, 85),
TEMP_PCT(85, 75),
TEMP_PCT(80, 65),
TEMP_PCT(75, 55),
TEMP_PCT(70, 45),}}"
.thresholds={TEMP_PCT(94, 0),}}"
register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0,
.thresholds={TEMP_PCT(50, 85),
TEMP_PCT(47, 75),
TEMP_PCT(45, 65),
TEMP_PCT(42, 55),
TEMP_PCT(39, 45),}}"
.thresholds={TEMP_PCT(65, 90),
TEMP_PCT(61, 80),
TEMP_PCT(57, 70),
TEMP_PCT(53, 60),
TEMP_PCT(49, 50),
TEMP_PCT(45, 40),
TEMP_PCT(41, 0),}}"
## Passive Policy
register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 93, 5000)"
register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 65, 6000)"
register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 5000)"
register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 68, 5000)"
## Critical Policy
register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)"
register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN)"
register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 78, SHUTDOWN)"
## Power Limits Control
# PL1 is fixed at 15W, avg over 28-32s interval
# 25-64W PL2 in 1000mW increments, avg over 28-32s interval
# 15-51W PL2 in 1000mW increments, avg over 28-32s interval
register "controls.power_limits.pl1" = "{
.min_power = 15000,
.max_power = 15000,
@ -301,8 +304,8 @@ chip soc/intel/cannonlake
.time_window_max = 32 * MSECS_PER_SEC,
.granularity = 200,}"
register "controls.power_limits.pl2" = "{
.min_power = 25000,
.max_power = 64000,
.min_power = 15000,
.max_power = 51000,
.time_window_min = 28 * MSECS_PER_SEC,
.time_window_max = 32 * MSECS_PER_SEC,
.granularity = 1000,}"

35
src/mainboard/google/hatch/variants/kaisa/overridetree.cb
View File

@ -1,6 +1,11 @@
chip soc/intel/cannonlake
register "tcc_offset" = "5" # TCC of 95C
register "power_limits_config" = "{
.tdp_pl1_override = 15,
.tdp_pl2_override = 51,
}"
# Auto-switch between X4 NVMe and X2 NVMe.
register "TetonGlacierMode" = "1"
@ -271,29 +276,27 @@ chip soc/intel/cannonlake
chip drivers/intel/dptf
## Active Policy
register "policies.active[0]" = "{.target=DPTF_CPU,
.thresholds={TEMP_PCT(90, 85),
TEMP_PCT(85, 75),
TEMP_PCT(80, 65),
TEMP_PCT(75, 55),
TEMP_PCT(70, 45),}}"
.thresholds={TEMP_PCT(94, 0),}}"
register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0,
.thresholds={TEMP_PCT(50, 85),
TEMP_PCT(47, 75),
TEMP_PCT(45, 65),
TEMP_PCT(42, 55),
TEMP_PCT(39, 45),}}"
.thresholds={TEMP_PCT(65, 90),
TEMP_PCT(61, 80),
TEMP_PCT(57, 70),
TEMP_PCT(53, 60),
TEMP_PCT(49, 50),
TEMP_PCT(45, 40),
TEMP_PCT(41, 0),}}"
## Passive Policy
register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 93, 5000)"
register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 65, 6000)"
register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 5000)"
register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 68, 5000)"
## Critical Policy
register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)"
register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN)"
register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 78, SHUTDOWN)"
## Power Limits Control
# PL1 is fixed at 15W, avg over 28-32s interval
# 25-64W PL2 in 1000mW increments, avg over 28-32s interval
# 15-51W PL2 in 1000mW increments, avg over 28-32s interval
register "controls.power_limits.pl1" = "{
.min_power = 15000,
.max_power = 15000,
@ -301,8 +304,8 @@ chip soc/intel/cannonlake
.time_window_max = 32 * MSECS_PER_SEC,
.granularity = 200,}"
register "controls.power_limits.pl2" = "{
.min_power = 25000,
.max_power = 64000,
.min_power = 15000,
.max_power = 51000,
.time_window_min = 28 * MSECS_PER_SEC,
.time_window_max = 32 * MSECS_PER_SEC,
.granularity = 1000,}"