* clean up all but two warnings on artecgroup dbe61
* integrate vsm init into normal x86.c code (so it can run above 1M) * call void main(unsigned long bist) except void cache_as_ram_main(void) on Geode LX (as we do on almost all other platforms now) * Unify Geode LX MSR setup (will bring most non-working LX targets back to life) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5471 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
Stefan Reinauer
parent
cf036d1266
commit
9839cbd53f
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@ -42,7 +42,7 @@ config GEODE_VSA
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config VSA_FILE
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string "AMD Geode GX2 VSA path and filename"
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depends on GEODE_VSA
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depends on GEODE_VSA && CPU_AMD_GX2
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default "gpl_vsa_gx_102.bin"
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help
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The path and filename of the file to use as VSA.
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@ -4,4 +4,3 @@ subdirs-y += ../../x86/cache
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subdirs-y += ../../x86/smm
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driver-y += model_gx2_init.o
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obj-y += cpubug.o
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obj-y += vsmsetup.o
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@ -1,222 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2000 Erik Arjan Hendriks
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* Copyright (C) 2000 Scyld Computing Corporation
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* Copyright (C) 2001 University of California. LA-CC Number 01-67.
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* Copyright (C) 2005 Nick.Barker9@btinternet.com
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* Copyright (C) 2007 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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*
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* LA-CC is the Los Alamos Control and Compliance Number, see also:
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* http://supply.lanl.gov/property/customs/eximguide/default.shtml
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <string.h>
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#include <cpu/cpu.h>
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#include <cpu/x86/lapic.h>
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#include <cpu/x86/cache.h>
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#include <arch/io.h>
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#include <cbfs.h>
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void do_vsmbios(void);
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#define VSA2_BUFFER 0x60000
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#define VSA2_ENTRY_POINT 0x60020
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#define VSA2_SIGNATURE 0x56534132 // 'VSA2' returned in EAX
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#define SIGNATURE 0x03
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/**
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* TODO.
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*
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* The address arguments to this function are PHYSICAL ADDRESSES!
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*
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* @param smm TODO.
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* @param sysm TODO.
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*/
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static void real_mode_switch_call_vsm(unsigned long smm, unsigned long sysm)
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{
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u16 entryHi = (VSA2_ENTRY_POINT & 0xffff0000) >> 4;
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u16 entryLo = (VSA2_ENTRY_POINT & 0xffff);
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__asm__ __volatile__(
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/* Paranoia -- does ecx get saved? not sure. This is
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* the easiest safe thing to do.
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*/
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" pushal \n"
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/* Save the stack. */
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" mov %%esp, __stack \n"
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" jmp 1f \n"
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"__stack: .long 0 \n"
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"1:\n"
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/* Get devfn into %%ecx. */
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" movl %%esp, %%ebp \n"
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/* Get the smm and sysm args into ecx and edx. */
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" movl %0, %%ecx \n"
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" movl %1, %%edx \n"
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/* Load 'our' gdt. */
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" lgdt %%cs:__mygdtaddr \n"
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/* This configures CS properly for real mode. */
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" ljmp $0x28, $__rms_16bit\n"
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"__rms_16bit: \n"
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" .code16 \n"
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/* 16 bit code from here on... */
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/* Load the segment registers with properly configured segment
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* descriptors. They will retain these configurations (limits,
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* writability, etc.) once protected mode is turned off.
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*/
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" mov $0x30, %%ax \n"
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" mov %%ax, %%ds \n"
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" mov %%ax, %%es \n"
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" mov %%ax, %%fs \n"
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" mov %%ax, %%gs \n"
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" mov %%ax, %%ss \n"
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/* Turn off protection (bit 0 in CR0). */
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" movl %%cr0, %%eax \n"
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" andl $0xFFFFFFFE, %%eax \n"
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" movl %%eax, %%cr0 \n"
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/* Now really going into real mode. */
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" ljmp $0, $__rms_real\n"
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"__rms_real: \n"
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/* Put the stack at the end of page zero.
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* That way we can easily share it between real and protected,
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* since the 16-bit ESP at segment 0 will work for any case.
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*/
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/* Setup a stack. */
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" mov $0x0, %%ax \n"
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" mov %%ax, %%ss \n"
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" movl $0x1000, %%eax \n"
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" movl %%eax, %%esp \n"
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/* Dump zeros in the other segregs. */
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" mov %%ax, %%es \n"
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/* FIXME: Big real mode for gs, fs? */
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" mov %%ax, %%fs \n"
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" mov %%ax, %%gs \n"
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" mov $0x40, %%ax \n"
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" mov %%ax, %%ds \n"
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/* " mov %%cx, %%ax \n" */
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" movl %0, %%ecx \n"
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" movl %1, %%edx \n"
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/* Call the VSA2 entry point address. */
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" lcall %2, %3\n"
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/* If we got here, just about done.
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* Need to get back to protected mode.
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*/
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" movl %%cr0, %%eax \n"
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" orl $0x0000001, %%eax\n" /* PE = 1 */
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" movl %%eax, %%cr0 \n"
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/* Now that we are in protected mode,
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* jump to a 32 bit code segment.
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*/
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" data32 ljmp $0x10, $vsmrestart\n"
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"vsmrestart:\n"
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" .code32\n"
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" movw $0x18, %%ax \n"
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" mov %%ax, %%ds \n"
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" mov %%ax, %%es \n"
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" mov %%ax, %%fs \n"
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" mov %%ax, %%gs \n"
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" mov %%ax, %%ss \n"
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/* Restore proper gdt. */
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" lgdt %%cs:gdtarg \n"
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".globl vsm_exit \n"
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"vsm_exit: \n"
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" mov __stack, %%esp \n"
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" popal \n"::
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"g" (smm), "g"(sysm), "g"(entryHi), "g"(entryLo)
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);
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}
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__asm__(".text\n" "real_mode_switch_end:\n");
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extern char real_mode_switch_end[];
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/* andrei: Some VSA virtual register helpers: raw read and MSR read. */
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static u32 VSA_vrRead(u16 classIndex)
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{
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unsigned eax, ebx, ecx, edx;
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asm volatile (
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"movw $0x0AC1C, %%dx \n"
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"orl $0x0FC530000, %%eax \n"
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"outl %%eax, %%dx \n"
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"addb $2, %%dl \n"
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"inw %%dx, %%ax \n"
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: "=a" (eax), "=b"(ebx), "=c"(ecx), "=d"(edx)
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: "a"(classIndex)
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);
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return eax;
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}
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static u32 VSA_msrRead(u32 msrAddr)
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{
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unsigned eax, ebx, ecx, edx;
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asm volatile (
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"movw $0x0AC1C, %%dx \n"
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"movl $0x0FC530007, %%eax \n"
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"outl %%eax, %%dx \n"
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"addb $2, %%dl \n"
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"inw %%dx, %%ax \n"
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: "=a" (eax), "=b"(ebx), "=c"(ecx), "=d"(edx)
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: "c"(msrAddr)
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);
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return eax;
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}
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void do_vsmbios(void)
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{
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unsigned char *buf;
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int i;
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printk(BIOS_ERR, "do_vsmbios\n");
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/* Clear VSM BIOS data area. */
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for (i = 0x400; i < 0x500; i++)
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*(volatile unsigned char *)i = 0;
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if ((unsigned int)cbfs_load_stage("vsa") != VSA2_ENTRY_POINT) {
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printk(BIOS_ERR, "do_vsmbios: Failed to load VSA.\n");
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}
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buf = VSA2_BUFFER;
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printk(BIOS_DEBUG, "buf[0x20] signature is %x:%x:%x:%x\n",
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buf[0x20], buf[0x21], buf[0x22], buf[0x23]);
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/* Check for POST code at start of vsainit.bin. If you don't see it,
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* don't bother.
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*/
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if ((buf[0x20] != 0xb0) || (buf[0x21] != 0x10) ||
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(buf[0x22] != 0xe6) || (buf[0x23] != 0x80)) {
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die("FATAL: no vsainit.bin signature, skipping!\n");
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}
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/* ecx gets smm, edx gets sysm. */
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printk(BIOS_ERR, "Call real_mode_switch_call_vsm\n");
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// real_mode_switch_call_vsm(MSR_GLIU0_SMM, MSR_GLIU0_SYSMEM);
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/* Restart Timer 1. */
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outb(0x56, 0x43);
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outb(0x12, 0x41);
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/* Check that VSA is running OK. */
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if (VSA_vrRead(SIGNATURE) == VSA2_SIGNATURE)
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printk(BIOS_DEBUG, "do_vsmbios: VSA2 VR signature verified\n");
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else
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die("FATAL: VSA2 VR signature not valid, install failed!\n");
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}
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@ -23,7 +23,7 @@ config GEODE_VSA
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config VSA_FILE
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string "AMD Geode LX VSA path and filename"
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depends on GEODE_VSA
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depends on GEODE_VSA && CPU_AMD_LX
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default "gpl_vsa_lx_102.bin"
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help
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The path and filename of the file to use as VSA.
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|
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@ -5,6 +5,5 @@ subdirs-y += ../../x86/smm
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driver-y += model_lx_init.o
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obj-y += cpubug.o
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obj-y += vsmsetup.o
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cpu_incs += $(src)/cpu/amd/model_lx/cache_as_ram.inc
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|
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@ -34,6 +34,8 @@
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/**
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/***************************************************************************/
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DCacheSetup:
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/* Save the BIST result */
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movl %eax, %ebx
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invd
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/* set cache properties */
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@ -173,9 +175,17 @@ DCacheSetupBad:
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hlt /* issues */
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jmp DCacheSetupBad
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DCacheSetupGood:
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/* Go do early init and memory setup */
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call cache_as_ram_main
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/* Restore the BIST result */
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movl %ebx, %eax
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movl %esp, %ebp
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pushl %eax
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post_code(0x23)
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/* Call romstage.c main function */
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call main
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done_cache_as_ram_main:
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/* We now run over the stack-in-cache, copying it back to itself to invalidate the cache */
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|
|
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|
|
@ -0,0 +1,53 @@
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/*
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* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 coresystems GmbH
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
struct msrinit {
|
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u32 msrnum;
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msr_t msr;
|
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};
|
||||
|
||||
static const struct msrinit msr_table[] =
|
||||
{
|
||||
{CPU_RCONF_DEFAULT, {.hi = 0x24fffc02,.lo = 0x1000A000}}, /* Setup access to cache under 1MB.
|
||||
* Rom Properties: Write Serialize, WriteProtect.
|
||||
* RomBase: 0xFFFC0
|
||||
* SysTop to RomBase Properties: Write Serialize, Cache Disable.
|
||||
* SysTop: 0x000A0
|
||||
* System Memory Properties: (Write Back) */
|
||||
{CPU_RCONF_A0_BF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xA0000-0xBFFFF : (Write Back) */
|
||||
{CPU_RCONF_C0_DF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xC0000-0xDFFFF : (Write Back) */
|
||||
{CPU_RCONF_E0_FF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xE0000-0xFFFFF : (Write Back) */
|
||||
|
||||
/* Setup access to memory under 1MB. Note: VGA hole at 0xA0000-0xBFFFF */
|
||||
{MSR_GLIU0_BASE1, {.hi = 0x20000000,.lo = 0x000fff80}}, // 0x00000-0x7FFFF
|
||||
{MSR_GLIU0_BASE2, {.hi = 0x20000000,.lo = 0x080fffe0}}, // 0x80000-0x9FFFF
|
||||
{MSR_GLIU0_SHADOW, {.hi = 0x2000FFFF,.lo = 0xFFFF0003}}, // 0xC0000-0xFFFFF
|
||||
{MSR_GLIU1_BASE1, {.hi = 0x20000000,.lo = 0x000fff80}}, // 0x00000-0x7FFFF
|
||||
{MSR_GLIU1_BASE2, {.hi = 0x20000000,.lo = 0x080fffe0}}, // 0x80000-0x9FFFF
|
||||
{MSR_GLIU1_SHADOW, {.hi = 0x2000FFFF,.lo = 0xFFFF0003}}, // 0xC0000-0xFFFFF
|
||||
};
|
||||
|
||||
static void msr_init(void)
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < ARRAY_SIZE(msr_table); i++)
|
||||
wrmsr(msr_table[i].msrnum, msr_table[i].msr);
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -1,764 +0,0 @@
|
|||
#include <console/console.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <device/pci_ops.h>
|
||||
#undef __KERNEL__
|
||||
#include <arch/io.h>
|
||||
#include <string.h>
|
||||
#include <cpu/amd/lxdef.h>
|
||||
#include <cpu/amd/vr.h>
|
||||
#include <cbfs.h>
|
||||
|
||||
#define VSA2_BUFFER 0x60000
|
||||
#define VSA2_ENTRY_POINT 0x60020
|
||||
|
||||
/* vsmsetup.c derived from vgabios.c. Derived from: */
|
||||
|
||||
/*------------------------------------------------------------ -*- C -*-
|
||||
* 2 Kernel Monte a.k.a. Linux loading Linux on x86
|
||||
*
|
||||
* Erik Arjan Hendriks <hendriks@lanl.gov>
|
||||
*
|
||||
* This version is a derivative of the original two kernel monte
|
||||
* which is (C) 2000 Scyld.
|
||||
*
|
||||
* Copyright (C) 2000 Scyld Computing Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
*
|
||||
* Portions related to the alpha architecture are:
|
||||
*
|
||||
* Copyright(C) 2001 University of California. LA-CC Number 01-67.
|
||||
* This software has been authored by an employee or employees of the
|
||||
* University of California, operator of the Los Alamos National
|
||||
* Laboratory under Contract No. W-7405-ENG-36 with the U.S.
|
||||
* Department of Energy. The U.S. Government has rights to use,
|
||||
* reproduce, and distribute this software. If the software is
|
||||
* modified to produce derivative works, such modified software should
|
||||
* be clearly marked, so as not to confuse it with the version
|
||||
* available from LANL.
|
||||
*
|
||||
* This software may be used and distributed according to the terms
|
||||
* of the GNU General Public License, incorporated herein by
|
||||
* reference to http://www.gnu.org/licenses/gpl.html.
|
||||
*
|
||||
* This software is provided by the author(s) "as is" and any express
|
||||
* or implied warranties, including, but not limited to, the implied
|
||||
* warranties of merchantability and fitness for a particular purpose
|
||||
* are disclaimed. In no event shall the author(s) be liable for any
|
||||
* direct, indirect, incidental, special, exemplary, or consequential
|
||||
* damages (including, but not limited to, procurement of substitute
|
||||
* goods or services; loss of use, data, or profits; or business
|
||||
* interruption) however caused and on any theory of liability,
|
||||
* whether in contract, strict liability, or tort (including
|
||||
* negligence or otherwise) arising in any way out of the use of this
|
||||
* software, even if advised of the possibility of such damage.
|
||||
*
|
||||
* $Id: vsmsetup.c,v 1.8 2006/09/08 12:47:57 andrei Exp $
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
*--------------------------------------------------------------------*/
|
||||
|
||||
/* Modified to be a self sufficient plug in so that it can be used
|
||||
without reliance on other parts of core coreboot
|
||||
(C) 2005 Nick.Barker9@btinternet.com
|
||||
|
||||
Used initially for epia-m where there are problems getting the bios
|
||||
emulator to successfully run this bios.
|
||||
*/
|
||||
|
||||
/* Declare a temporary global descriptor table - necessary because the
|
||||
Core part of the bios no longer sets up any 16 bit segments */
|
||||
__asm__(
|
||||
/* pointer to original gdt */
|
||||
"gdtarg: \n"
|
||||
" .word gdt_limit \n"
|
||||
" .long gdt \n"
|
||||
/* compute the table limit */
|
||||
"__mygdt_limit = __mygdt_end - __mygdt - 1 \n"
|
||||
"__mygdtaddr: \n"
|
||||
" .word __mygdt_limit \n"
|
||||
" .long __mygdt \n"
|
||||
"__mygdt: \n"
|
||||
/* selgdt 0, unused */
|
||||
" .word 0x0000, 0x0000 \n"
|
||||
" .byte 0x00, 0x00, 0x00, 0x00 \n"
|
||||
/* selgdt 8, unused */
|
||||
" .word 0x0000, 0x0000 \n"
|
||||
" .byte 0x00, 0x00, 0x00, 0x00 \n"
|
||||
/* selgdt 0x10, flat code segment */
|
||||
" .word 0xffff, 0x0000 \n"
|
||||
" .byte 0x00, 0x9b, 0xcf, 0x00 \n"
|
||||
/* selgdt 0x18, flat data segment */
|
||||
" .word 0xffff, 0x0000 \n"
|
||||
" .byte 0x00, 0x93, 0xcf, 0x00 \n"
|
||||
/* selgdt 0x20, unused */
|
||||
" .word 0x0000, 0x0000 \n"
|
||||
" .byte 0x00, 0x00, 0x00, 0x00 \n"
|
||||
/* selgdt 0x28 16-bit 64k code at 0x00000000 */
|
||||
" .word 0xffff, 0x0000 \n"
|
||||
" .byte 0, 0x9a, 0, 0 \n"
|
||||
/* selgdt 0x30 16-bit 64k data at 0x00000000 */
|
||||
" .word 0xffff, 0x0000 \n"
|
||||
" .byte 0, 0x92, 0, 0 \n"
|
||||
"__mygdt_end: \n"
|
||||
);
|
||||
|
||||
/* Declare a pointer to where our idt is going to be i.e. at mem zero */
|
||||
__asm__(
|
||||
"__myidt: \n"
|
||||
/* 16-bit limit */
|
||||
" .word 1023 \n"
|
||||
/* 24-bit base */
|
||||
" .long 0 \n"
|
||||
" .word 0 \n"
|
||||
);
|
||||
|
||||
/* The address arguments to this function are PHYSICAL ADDRESSES */
|
||||
static void real_mode_switch_call_vsm(unsigned long smm, unsigned long sysm)
|
||||
{
|
||||
uint16_t entryHi = (VSA2_ENTRY_POINT & 0xffff0000) >> 4;
|
||||
uint16_t entryLo = (VSA2_ENTRY_POINT & 0xffff);
|
||||
|
||||
__asm__ __volatile__(
|
||||
// paranoia -- does ecx get saved? not sure. This is
|
||||
// the easiest safe thing to do.
|
||||
" pushal \n"
|
||||
/* save the stack */
|
||||
" mov %%esp, __stack \n"
|
||||
" jmp 1f \n"
|
||||
"__stack: .long 0 \n"
|
||||
"1:\n"
|
||||
/* get devfn into %%ecx */
|
||||
" movl %%esp, %%ebp \n"
|
||||
#if 0
|
||||
/* I'm not happy about that pushal followed by esp-relative
|
||||
* references. Just do hard-codes for now
|
||||
*/
|
||||
" movl 8(%%ebp), %%ecx \n"
|
||||
" movl 12(%%ebp), %%edx \n"
|
||||
#endif
|
||||
" movl %0, %%ecx \n"
|
||||
" movl %1, %%edx \n"
|
||||
/* load 'our' gdt */
|
||||
" lgdt %%cs:__mygdtaddr \n"
|
||||
/* This configures CS properly for real mode. */
|
||||
" ljmp $0x28, $__rms_16bit\n"
|
||||
"__rms_16bit: \n"
|
||||
" .code16 \n"
|
||||
/* 16 bit code from here on... */
|
||||
/* Load the segment registers w/ properly configured segment
|
||||
* descriptors. They will retain these configurations (limits,
|
||||
* writability, etc.) once protected mode is turned off. */
|
||||
" mov $0x30, %%ax \n"
|
||||
" mov %%ax, %%ds \n"
|
||||
" mov %%ax, %%es \n"
|
||||
" mov %%ax, %%fs \n"
|
||||
" mov %%ax, %%gs \n"
|
||||
" mov %%ax, %%ss \n"
|
||||
/* Turn off protection (bit 0 in CR0) */
|
||||
" movl %%cr0, %%eax \n"
|
||||
" andl $0xFFFFFFFE, %%eax \n"
|
||||
" movl %%eax, %%cr0 \n"
|
||||
/* Now really going into real mode */
|
||||
" ljmp $0, $__rms_real\n"
|
||||
"__rms_real: \n"
|
||||
|
||||
/* put the stack at the end of page zero.
|
||||
* that way we can easily share it between real and protected,
|
||||
* since the 16-bit ESP at segment 0 will work for any case.
|
||||
*/
|
||||
|
||||
/* Setup a stack */
|
||||
" mov $0x0, %%ax \n"
|
||||
" mov %%ax, %%ss \n"
|
||||
" movl $0x1000, %%eax \n"
|
||||
" movl %%eax, %%esp \n"
|
||||
/* Load our 16 it idt */
|
||||
" xor %%ax, %%ax \n"
|
||||
" mov %%ax, %%ds \n"
|
||||
" lidt __myidt \n"
|
||||
/* Dump zeros in the other segregs */
|
||||
" mov %%ax, %%es \n"
|
||||
/* FixMe: Big real mode for gs, fs? */
|
||||
" mov %%ax, %%fs \n"
|
||||
" mov %%ax, %%gs \n"
|
||||
" mov $0x40, %%ax \n"
|
||||
" mov %%ax, %%ds \n"
|
||||
//" mov %%cx, %%ax \n"
|
||||
" movl %0, %%ecx \n"
|
||||
" movl %1, %%edx \n"
|
||||
/* call the VSA2 entry point address */
|
||||
" lcall %2, %3\n"
|
||||
/* if we got here, just about done.
|
||||
* Need to get back to protected mode */
|
||||
" movl %%cr0, %%eax \n"
|
||||
" orl $0x0000001, %%eax\n" /* PE = 1 */
|
||||
" movl %%eax, %%cr0 \n"
|
||||
/* Now that we are in protected mode jump to a 32 bit code segment. */
|
||||
" data32 ljmp $0x10, $vsmrestart\n"
|
||||
"vsmrestart:\n"
|
||||
" .code32\n"
|
||||
" movw $0x18, %%ax \n"
|
||||
" mov %%ax, %%ds \n"
|
||||
" mov %%ax, %%es \n"
|
||||
" mov %%ax, %%fs \n"
|
||||
" mov %%ax, %%gs \n"
|
||||
" mov %%ax, %%ss \n"
|
||||
/* restore proper gdt and idt */
|
||||
" lgdt %%cs:gdtarg \n"
|
||||
" lidt idtarg \n"
|
||||
".globl vsm_exit \n"
|
||||
"vsm_exit: \n"
|
||||
" mov __stack, %%esp \n"
|
||||
" popal \n"::
|
||||
"g" (smm), "g"(sysm), "g"(entryHi), "g"(entryLo)
|
||||
);
|
||||
}
|
||||
|
||||
__asm__(".text\n" "real_mode_switch_end:\n");
|
||||
extern char real_mode_switch_end[];
|
||||
|
||||
// andrei: some VSA virtual register helpers: raw read and MSR read
|
||||
|
||||
uint32_t VSA_vrRead(uint16_t classIndex)
|
||||
{
|
||||
unsigned eax, ebx, ecx, edx;
|
||||
asm volatile (
|
||||
"movw $0x0AC1C, %%dx \n"
|
||||
"orl $0x0FC530000, %%eax \n"
|
||||
"outl %%eax, %%dx \n"
|
||||
"addb $2, %%dl \n"
|
||||
"inw %%dx, %%ax \n"
|
||||
: "=a" (eax), "=b"(ebx), "=c"(ecx), "=d"(edx)
|
||||
: "a"(classIndex)
|
||||
);
|
||||
|
||||
return eax;
|
||||
}
|
||||
|
||||
uint32_t VSA_msrRead(uint32_t msrAddr)
|
||||
{
|
||||
unsigned eax, ebx, ecx, edx;
|
||||
asm volatile (
|
||||
"movw $0x0AC1C, %%dx \n"
|
||||
"movl $0x0FC530007, %%eax \n"
|
||||
"outl %%eax, %%dx \n"
|
||||
"addb $2, %%dl \n"
|
||||
"inw %%dx, %%ax \n"
|
||||
: "=a" (eax), "=b"(ebx), "=c"(ecx), "=d"(edx)
|
||||
: "c"(msrAddr)
|
||||
);
|
||||
|
||||
return eax;
|
||||
}
|
||||
|
||||
void do_vsmbios(void)
|
||||
{
|
||||
unsigned char *buf;
|
||||
int i;
|
||||
|
||||
printk(BIOS_ERR, "do_vsmbios\n");
|
||||
/* clear vsm bios data area */
|
||||
for (i = 0x400; i < 0x500; i++) {
|
||||
*(volatile unsigned char *)i = 0;
|
||||
}
|
||||
|
||||
/* declare rom address here - keep any config data out of the way
|
||||
* of core LXB stuff */
|
||||
|
||||
/* this is the base of rom on the LX at present. At some point, this has to be
|
||||
* much better parameterized
|
||||
*/
|
||||
|
||||
if ((unsigned int)cbfs_load_stage("vsa") != VSA2_ENTRY_POINT) {
|
||||
printk(BIOS_ERR, "do_vsmbios: Failed to load VSA.\n");
|
||||
}
|
||||
buf = (unsigned char *)VSA2_BUFFER;
|
||||
printk(BIOS_DEBUG, "buf %p *buf %d buf[256k] %d\n",
|
||||
buf, buf[0], buf[SMM_SIZE * 1024]);
|
||||
printk(BIOS_DEBUG, "buf[0x20] signature is %x:%x:%x:%x\n",
|
||||
buf[0x20], buf[0x21], buf[0x22], buf[0x23]);
|
||||
/* check for post code at start of vsainit.bin. If you don't see it,
|
||||
don't bother. */
|
||||
if ((buf[0x20] != 0xb0) || (buf[0x21] != 0x10) ||
|
||||
(buf[0x22] != 0xe6) || (buf[0x23] != 0x80)) {
|
||||
printk(BIOS_ERR, "do_vsmbios: no vsainit.bin signature, skipping!\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/* ecx gets smm, edx gets sysm */
|
||||
printk(BIOS_ERR, "Call real_mode_switch_call_vsm\n");
|
||||
real_mode_switch_call_vsm(MSR_GLIU0_SMM, MSR_GLIU0_SYSMEM);
|
||||
|
||||
/* restart timer 1 */
|
||||
outb(0x56, 0x43);
|
||||
outb(0x12, 0x41);
|
||||
|
||||
// check that VSA is running OK
|
||||
if (VSA_vrRead(SIGNATURE) == VSA2_SIGNATURE)
|
||||
printk(BIOS_DEBUG, "do_vsmbios: VSA2 VR signature verified\n");
|
||||
else
|
||||
printk(BIOS_ERR, "do_vsmbios: VSA2 VR signature not valid, install failed!\n");
|
||||
}
|
||||
|
||||
// we had hoped to avoid this.
|
||||
// this is a stub IDT only. It's main purpose is to ignore calls
|
||||
// to the BIOS.
|
||||
// no longer. Dammit. We have to respond to these.
|
||||
struct realidt {
|
||||
unsigned short offset, cs;
|
||||
};
|
||||
|
||||
// from a handy writeup that andrey found.
|
||||
|
||||
// handler.
|
||||
// There are some assumptions we can make here.
|
||||
// First, the Top Of Stack (TOS) is located on the top of page zero.
|
||||
// we can share this stack between real and protected mode.
|
||||
// that simplifies a lot of things ...
|
||||
// we'll just push all the registers on the stack as longwords,
|
||||
// and pop to protected mode.
|
||||
// second, since this only ever runs as part of coreboot,
|
||||
// we know all the segment register values -- so we don't save any.
|
||||
// keep the handler that calls things small. It can do a call to
|
||||
// more complex code in coreboot itself. This helps a lot as we don't
|
||||
// have to do address fixup in this little stub, and calls are absolute
|
||||
// so the handler is relocatable.
|
||||
void handler(void)
|
||||
{
|
||||
__asm__ __volatile__(
|
||||
" .code16 \n"
|
||||
"idthandle: \n"
|
||||
" pushal \n"
|
||||
" movb $0, %al \n"
|
||||
" ljmp $0, $callbiosint16\n"
|
||||
"end_idthandle: \n"
|
||||
" .code32 \n"
|
||||
);
|
||||
}
|
||||
|
||||
void debughandler(void)
|
||||
{
|
||||
__asm__ __volatile__(
|
||||
" .code16 \n"
|
||||
"debughandle: \n"
|
||||
" pushw %cx \n"
|
||||
" movw $250, %cx \n"
|
||||
"dbh1: \n"
|
||||
" loop dbh1 \n"
|
||||
" popw %cx \n"
|
||||
" iret \n"
|
||||
"end_debughandle: \n"
|
||||
".code32 \n"
|
||||
);
|
||||
}
|
||||
|
||||
// Calling conventions. The first C function is called with this stuff
|
||||
// on the stack. They look like value parameters, but note that if you
|
||||
// modify them they will go back to the INTx function modified.
|
||||
// the C function will call the biosint function with these as
|
||||
// REFERENCE parameters. In this way, we can easily get
|
||||
// returns back to the INTx caller (i.e. vgabios)
|
||||
void callbiosint(void)
|
||||
{
|
||||
__asm__ __volatile__(
|
||||
" .code16 \n"
|
||||
"callbiosint16: \n"
|
||||
" push %ds \n"
|
||||
" push %es \n"
|
||||
" push %fs \n"
|
||||
" push %gs \n"
|
||||
// clean up the int #. To save space we put it in the lower
|
||||
// byte. But the top 24 bits are junk.
|
||||
" andl $0xff, %eax\n"
|
||||
// this push does two things:
|
||||
// - put the INT # on the stack as a parameter
|
||||
// - provides us with a temp for the %cr0 mods.
|
||||
" pushl %eax \n"
|
||||
" movb $0xbb, %al\n"
|
||||
" outb %al, $0x80\n"
|
||||
" movl %cr0, %eax\n"
|
||||
" orl $0x00000001, %eax\n" /* PE = 1 */
|
||||
" movl %eax, %cr0\n"
|
||||
/* Now that we are in protected mode jump to a 32 bit code segment. */
|
||||
" data32 ljmp $0x10, $biosprotect\n"
|
||||
"biosprotect: \n"
|
||||
" .code32 \n"
|
||||
" movw $0x18, %ax\n"
|
||||
" mov %ax, %ds\n"
|
||||
" mov %ax, %es\n"
|
||||
" mov %ax, %fs\n"
|
||||
" mov %ax, %gs\n"
|
||||
" mov %ax, %ss\n"
|
||||
" lidt idtarg \n"
|
||||
" call biosint \n"
|
||||
// back to real mode ...
|
||||
" ljmp $0x28, $__rms_16bit2\n"
|
||||
"__rms_16bit2: \n"
|
||||
" .code16 \n"
|
||||
/* 16 bit code from here on... */
|
||||
/* Load the segment registers w/ properly configured segment
|
||||
* descriptors. They will retain these configurations (limits,
|
||||
* writability, etc.) once protected mode is turned off. */
|
||||
" mov $0x30, %ax\n"
|
||||
" mov %ax, %ds\n"
|
||||
" mov %ax, %es\n"
|
||||
" mov %ax, %fs\n"
|
||||
" mov %ax, %gs\n"
|
||||
" mov %ax, %ss\n"
|
||||
/* Turn off protection (bit 0 in CR0) */
|
||||
" movl %cr0, %eax \n"
|
||||
" andl $0xFFFFFFFE, %eax \n"
|
||||
" movl %eax, %cr0 \n"
|
||||
/* Now really going into real mode */
|
||||
" ljmp $0, $__rms_real2 \n"
|
||||
"__rms_real2: \n"
|
||||
/* Setup a stack
|
||||
* FixME: where is esp? */
|
||||
/* no need for a fix here. The esp is shared from 32-bit and 16-bit mode.
|
||||
* you have to hack on the ss, but the esp remains the same across
|
||||
* modes.
|
||||
*/
|
||||
" mov $0x0, %ax \n"
|
||||
" mov %ax, %ss \n"
|
||||
/* debugging for RGM */
|
||||
" mov $0x11, %al \n"
|
||||
" outb %al, $0x80 \n"
|
||||
/* Load our 16 bit idt */
|
||||
" xor %ax, %ax \n"
|
||||
" mov %ax, %ds \n"
|
||||
" lidt __myidt \n"
|
||||
/* Dump zeros in the other segregs */
|
||||
" mov %ax, %es \n"
|
||||
" mov %ax, %fs \n"
|
||||
" mov %ax, %gs \n"
|
||||
" mov $0x40, %ax \n"
|
||||
" mov %ax, %ds \n"
|
||||
/* pop the INT # that you pushed earlier */
|
||||
" popl %eax \n"
|
||||
" pop %gs \n"
|
||||
" pop %fs \n"
|
||||
" pop %es \n"
|
||||
" pop %ds \n"
|
||||
" popal \n"
|
||||
" iret \n"
|
||||
" .code32 \n"
|
||||
);
|
||||
}
|
||||
|
||||
enum {
|
||||
PCIBIOS = 0x1a,
|
||||
MEMSIZE = 0x12
|
||||
};
|
||||
|
||||
int pcibios(unsigned long *pedi, unsigned long *pesi, unsigned long *pebp,
|
||||
unsigned long *pesp, unsigned long *pebx, unsigned long *pedx,
|
||||
unsigned long *pecx, unsigned long *peax, unsigned long *pflags);
|
||||
|
||||
int handleint21(unsigned long *pedi, unsigned long *pesi, unsigned long *pebp,
|
||||
unsigned long *pesp, unsigned long *pebx, unsigned long *pedx,
|
||||
unsigned long *pecx, unsigned long *peax,
|
||||
unsigned long *pflags);
|
||||
|
||||
int biosint(unsigned long intnumber,
|
||||
unsigned long gsfs, unsigned long dses,
|
||||
unsigned long edi, unsigned long esi,
|
||||
unsigned long ebp, unsigned long esp,
|
||||
unsigned long ebx, unsigned long edx,
|
||||
unsigned long ecx, unsigned long eax,
|
||||
unsigned long cs_ip, unsigned short stackflags)
|
||||
{
|
||||
unsigned long ip;
|
||||
unsigned long cs;
|
||||
unsigned long flags;
|
||||
int ret = -1;
|
||||
|
||||
ip = cs_ip & 0xffff;
|
||||
cs = cs_ip >> 16;
|
||||
flags = stackflags;
|
||||
|
||||
printk(BIOS_DEBUG, "biosint: INT# 0x%lx\n", intnumber);
|
||||
printk(BIOS_DEBUG, "biosint: eax 0x%lx ebx 0x%lx ecx 0x%lx edx 0x%lx\n",
|
||||
eax, ebx, ecx, edx);
|
||||
printk(BIOS_DEBUG, "biosint: ebp 0x%lx esp 0x%lx edi 0x%lx esi 0x%lx\n",
|
||||
ebp, esp, edi, esi);
|
||||
printk(BIOS_DEBUG, "biosint: ip 0x%x cs 0x%x flags 0x%x\n",
|
||||
(u32)ip, (u32)cs, (u32)flags);
|
||||
printk(BIOS_DEBUG, "biosint: gs 0x%x fs 0x%x ds 0x%x es 0x%x\n",
|
||||
(u16)(gsfs >> 16), (u16)(gsfs & 0xffff), (u16)(dses >> 16), (u16)(dses & 0xffff));
|
||||
|
||||
// cases in a good compiler are just as good as your own tables.
|
||||
switch (intnumber) {
|
||||
case 0 ... 15:
|
||||
// These are not BIOS service, but the CPU-generated exceptions
|
||||
printk(BIOS_INFO, "biosint: Oops, exception 0x%x\n", (u32)intnumber);
|
||||
if (esp < 0x1000) {
|
||||
printk(BIOS_DEBUG, "Stack contents: ");
|
||||
while (esp < 0x1000) {
|
||||
printk(BIOS_DEBUG, "0x%04x ", *(unsigned short *)esp);
|
||||
esp += 2;
|
||||
}
|
||||
printk(BIOS_DEBUG, "\n");
|
||||
}
|
||||
printk(BIOS_DEBUG, "biosint: Bailing out ... not now\n");
|
||||
// "longjmp"
|
||||
//vga_exit();
|
||||
break;
|
||||
|
||||
case PCIBIOS:
|
||||
ret = pcibios(&edi, &esi, &ebp, &esp,
|
||||
&ebx, &edx, &ecx, &eax, &flags);
|
||||
break;
|
||||
case MEMSIZE:
|
||||
// who cares.
|
||||
eax = 128 * 1024;
|
||||
ret = 0;
|
||||
break;
|
||||
case 0x15:
|
||||
ret = handleint21(&edi, &esi, &ebp, &esp,
|
||||
&ebx, &edx, &ecx, &eax, &flags);
|
||||
break;
|
||||
default:
|
||||
printk(BIOS_INFO, "BIOSINT: Unsupported int #0x%x\n", (u32)intnumber);
|
||||
break;
|
||||
}
|
||||
if (ret)
|
||||
flags |= 1; // carry flags
|
||||
else
|
||||
flags &= ~1;
|
||||
stackflags = flags;
|
||||
return ret;
|
||||
}
|
||||
|
||||
void setup_realmode_idt(void)
|
||||
{
|
||||
extern unsigned char idthandle, end_idthandle;
|
||||
extern unsigned char debughandle, end_debughandle;
|
||||
|
||||
int i;
|
||||
struct realidt *idts = (struct realidt *)0;
|
||||
int codesize = &end_idthandle - &idthandle;
|
||||
unsigned char *intbyte, *codeptr;
|
||||
|
||||
// for each int, we create a customized little handler
|
||||
// that just pushes %ax, puts the int # in %al,
|
||||
// then calls the common interrupt handler.
|
||||
// this necessitated because intel didn't know much about
|
||||
// architecture when they did the 8086 (it shows)
|
||||
// (hmm do they know anymore even now :-)
|
||||
// obviously you can see I don't really care about memory
|
||||
// efficiency. If I did I would probe back through the stack
|
||||
// and get it that way. But that's really disgusting.
|
||||
for (i = 0; i < 256; i++) {
|
||||
idts[i].cs = 0;
|
||||
codeptr = (unsigned char *)4096 + i * codesize;
|
||||
idts[i].offset = (unsigned)codeptr;
|
||||
memcpy(codeptr, &idthandle, codesize);
|
||||
intbyte = codeptr + 3;
|
||||
*intbyte = i;
|
||||
}
|
||||
|
||||
// fixed entry points
|
||||
|
||||
// VGA BIOSes tend to hardcode f000:f065 as the previous handler of
|
||||
// int10.
|
||||
// calling convention here is the same as INTs, we can reuse
|
||||
// the int entry code.
|
||||
codeptr = (unsigned char *)0xff065;
|
||||
memcpy(codeptr, &idthandle, codesize);
|
||||
intbyte = codeptr + 3;
|
||||
*intbyte = 0x42; /* int42 is the relocated int10 */
|
||||
|
||||
/* debug handler - useful to set a programmable delay between instructions if the
|
||||
TF bit is set upon call to real mode */
|
||||
idts[1].cs = 0;
|
||||
idts[1].offset = 16384;
|
||||
memcpy((void *)16384, &debughandle, &end_debughandle - &debughandle);
|
||||
}
|
||||
|
||||
enum {
|
||||
CHECK = 0xb001,
|
||||
FINDDEV = 0xb102,
|
||||
READCONFBYTE = 0xb108,
|
||||
READCONFWORD = 0xb109,
|
||||
READCONFDWORD = 0xb10a,
|
||||
WRITECONFBYTE = 0xb10b,
|
||||
WRITECONFWORD = 0xb10c,
|
||||
WRITECONFDWORD = 0xb10d
|
||||
};
|
||||
|
||||
// errors go in AH. Just set these up so that word assigns
|
||||
// will work. KISS.
|
||||
enum {
|
||||
PCIBIOS_NODEV = 0x8600,
|
||||
PCIBIOS_BADREG = 0x8700
|
||||
};
|
||||
|
||||
int
|
||||
pcibios(unsigned long *pedi, unsigned long *pesi, unsigned long *pebp,
|
||||
unsigned long *pesp, unsigned long *pebx, unsigned long *pedx,
|
||||
unsigned long *pecx, unsigned long *peax, unsigned long *pflags)
|
||||
{
|
||||
unsigned short func = (unsigned short)*peax;
|
||||
int retval = 0;
|
||||
unsigned short devid, vendorid, devfn;
|
||||
short devindex; /* Use short to get rid of gabage in upper half of 32-bit register */
|
||||
unsigned char bus;
|
||||
device_t dev;
|
||||
|
||||
switch (func) {
|
||||
case CHECK:
|
||||
*pedx = 0x4350;
|
||||
*pecx = 0x2049;
|
||||
retval = 0;
|
||||
break;
|
||||
case FINDDEV:
|
||||
{
|
||||
devid = *pecx;
|
||||
vendorid = *pedx;
|
||||
devindex = *pesi;
|
||||
dev = 0;
|
||||
while ((dev = dev_find_device(vendorid, devid, dev))) {
|
||||
if (devindex <= 0)
|
||||
break;
|
||||
devindex--;
|
||||
}
|
||||
if (dev) {
|
||||
unsigned short busdevfn;
|
||||
*peax = 0;
|
||||
// busnum is an unsigned char;
|
||||
// devfn is an int, so we mask it off.
|
||||
busdevfn = (dev->bus->secondary << 8)
|
||||
| (dev->path.pci.devfn & 0xff);
|
||||
printk(BIOS_DEBUG, "0x%x: return 0x%x\n", func,
|
||||
busdevfn);
|
||||
*pebx = busdevfn;
|
||||
retval = 0;
|
||||
} else {
|
||||
*peax = PCIBIOS_NODEV;
|
||||
retval = -1;
|
||||
}
|
||||
}
|
||||
break;
|
||||
case READCONFDWORD:
|
||||
case READCONFWORD:
|
||||
case READCONFBYTE:
|
||||
case WRITECONFDWORD:
|
||||
case WRITECONFWORD:
|
||||
case WRITECONFBYTE:
|
||||
{
|
||||
unsigned long dword;
|
||||
unsigned short word;
|
||||
unsigned char byte;
|
||||
unsigned char reg;
|
||||
|
||||
devfn = *pebx & 0xff;
|
||||
bus = *pebx >> 8;
|
||||
reg = *pedi;
|
||||
dev = dev_find_slot(bus, devfn);
|
||||
if (!dev) {
|
||||
printk(BIOS_DEBUG, "0x%x: BAD DEVICE bus %d devfn 0x%x\n",
|
||||
func, bus, devfn);
|
||||
// idiots. the pcibios guys assumed you'd never pass a bad bus/devfn!
|
||||
*peax = PCIBIOS_BADREG;
|
||||
retval = -1;
|
||||
}
|
||||
switch (func) {
|
||||
case READCONFBYTE:
|
||||
byte = pci_read_config8(dev, reg);
|
||||
*pecx = byte;
|
||||
break;
|
||||
case READCONFWORD:
|
||||
word = pci_read_config16(dev, reg);
|
||||
*pecx = word;
|
||||
break;
|
||||
case READCONFDWORD:
|
||||
dword = pci_read_config32(dev, reg);
|
||||
*pecx = dword;
|
||||
break;
|
||||
case WRITECONFBYTE:
|
||||
byte = *pecx;
|
||||
pci_write_config8(dev, reg, byte);
|
||||
break;
|
||||
case WRITECONFWORD:
|
||||
word = *pecx;
|
||||
pci_write_config16(dev, reg, word);
|
||||
break;
|
||||
case WRITECONFDWORD:
|
||||
dword = *pecx;
|
||||
pci_write_config32(dev, reg, dword);
|
||||
break;
|
||||
}
|
||||
|
||||
if (retval)
|
||||
retval = PCIBIOS_BADREG;
|
||||
printk(BIOS_DEBUG, "0x%x: bus %d devfn 0x%x reg 0x%x val 0x%lx\n",
|
||||
func, bus, devfn, reg, *pecx);
|
||||
*peax = 0;
|
||||
retval = 0;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
printk(BIOS_ERR, "UNSUPPORTED PCIBIOS FUNCTION 0x%x\n", func);
|
||||
break;
|
||||
}
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
int handleint21(unsigned long *edi, unsigned long *esi, unsigned long *ebp,
|
||||
unsigned long *esp, unsigned long *ebx, unsigned long *edx,
|
||||
unsigned long *ecx, unsigned long *eax, unsigned long *flags)
|
||||
{
|
||||
int res = -1;
|
||||
printk(BIOS_DEBUG, "handleint21, eax 0x%x\n", (u32)*eax);
|
||||
switch (*eax & 0xffff) {
|
||||
case 0x5f19:
|
||||
break;
|
||||
case 0x5f18:
|
||||
*eax = 0x5f;
|
||||
*ebx = 0x545; // MCLK = 133, 32M frame buffer, 256 M main memory
|
||||
*ecx = 0x060;
|
||||
res = 0;
|
||||
break;
|
||||
case 0x5f00:
|
||||
*eax = 0x8600;
|
||||
break;
|
||||
case 0x5f01:
|
||||
*eax = 0x5f;
|
||||
*ecx = (*ecx & 0xffffff00) | 2; // panel type = 2 = 1024 * 768
|
||||
res = 0;
|
||||
break;
|
||||
case 0x5f02:
|
||||
*eax = 0x5f;
|
||||
*ebx = (*ebx & 0xffff0000) | 2;
|
||||
*ecx = (*ecx & 0xffff0000) | 0x401; // PAL + crt only
|
||||
*edx = (*edx & 0xffff0000) | 0; // TV Layout - default
|
||||
res = 0;
|
||||
break;
|
||||
case 0x5f0f:
|
||||
*eax = 0x860f;
|
||||
break;
|
||||
case 0xBEA7:
|
||||
*eax = 66;
|
||||
break;
|
||||
case 0xBEA4:
|
||||
*eax = 500;
|
||||
break;
|
||||
}
|
||||
return res;
|
||||
}
|
||||
|
|
@ -1,7 +1,8 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2009 coresystems GmbH
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
* Copyright (C) 2009-2010 coresystems GmbH
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
|
|
@ -36,9 +37,11 @@ void x86_exception(struct eregs *info);
|
|||
extern unsigned char __idt_handler, __idt_handler_size;
|
||||
extern unsigned char __realmode_code, __realmode_code_size;
|
||||
extern unsigned char __run_optionrom, __run_interrupt;
|
||||
extern unsigned char __run_vsa;
|
||||
|
||||
void (*run_optionrom)(u32 devfn) __attribute__((regparm(0))) = (void *)&__run_optionrom;
|
||||
void (*vga_enable_console)(void) __attribute__((regparm(0))) = (void *)&__run_interrupt;
|
||||
void (*run_vsa)(u32 smm, u32 sysmem) __attribute__((regparm(0))) = (void *)&__run_vsa;
|
||||
|
||||
int (*intXX_handler[256])(struct eregs *regs) = { NULL };
|
||||
|
||||
|
|
@ -160,6 +163,88 @@ void run_bios(struct device *dev, unsigned long addr)
|
|||
printk(BIOS_DEBUG, "... Option ROM returned.\n");
|
||||
}
|
||||
|
||||
#if defined(CONFIG_GEODE_VSA) && CONFIG_GEODE_VSA
|
||||
#include <cpu/amd/lxdef.h>
|
||||
#include <cpu/amd/vr.h>
|
||||
#include <cbfs.h>
|
||||
|
||||
#define VSA2_BUFFER 0x60000
|
||||
#define VSA2_ENTRY_POINT 0x60020
|
||||
|
||||
// TODO move to a header file.
|
||||
void do_vsmbios(void);
|
||||
|
||||
/* VSA virtual register helper */
|
||||
static u32 VSA_vrRead(u16 classIndex)
|
||||
{
|
||||
u32 eax, ebx, ecx, edx;
|
||||
asm volatile (
|
||||
"movw $0x0AC1C, %%dx\n"
|
||||
"orl $0x0FC530000, %%eax\n"
|
||||
"outl %%eax, %%dx\n"
|
||||
"addb $2, %%dl\n"
|
||||
"inw %%dx, %%ax\n"
|
||||
: "=a" (eax), "=b"(ebx), "=c"(ecx), "=d"(edx)
|
||||
: "a"(classIndex)
|
||||
);
|
||||
|
||||
return eax;
|
||||
}
|
||||
|
||||
void do_vsmbios(void)
|
||||
{
|
||||
printk(BIOS_DEBUG, "Preparing for VSA...\n");
|
||||
|
||||
/* clear bios data area */
|
||||
memset((void *)0x400, 0, 0x200);
|
||||
|
||||
/* Set up C interrupt handlers */
|
||||
setup_interrupt_handlers();
|
||||
|
||||
/* Setting up realmode IDT */
|
||||
setup_realmode_idt();
|
||||
|
||||
memcpy(REALMODE_BASE, &__realmode_code, (size_t)&__realmode_code_size);
|
||||
printk(BIOS_SPEW, "VSA: Real mode stub @%p: %d bytes\n", REALMODE_BASE,
|
||||
(u32)&__realmode_code_size);
|
||||
|
||||
if ((unsigned int)cbfs_load_stage("vsa") != VSA2_ENTRY_POINT) {
|
||||
printk(BIOS_ERR, "Failed to load VSA.\n");
|
||||
return;
|
||||
}
|
||||
|
||||
unsigned char *buf = (unsigned char *)VSA2_BUFFER;
|
||||
printk(BIOS_DEBUG, "VSA: Buffer @%p *[0k]=%02x\n", buf, buf[0]);
|
||||
printk(BIOS_DEBUG, "VSA: Signature *[0x20-0x23] is %02x:%02x:%02x:%02x\n",
|
||||
buf[0x20], buf[0x21], buf[0x22], buf[0x23]);
|
||||
|
||||
/* Check for code to emit POST code at start of VSA. */
|
||||
if ((buf[0x20] != 0xb0) || (buf[0x21] != 0x10) ||
|
||||
(buf[0x22] != 0xe6) || (buf[0x23] != 0x80)) {
|
||||
printk(BIOS_WARNING, "VSA: Signature incorrect. Install failed.\n");
|
||||
return;
|
||||
}
|
||||
|
||||
printk(BIOS_DEBUG, "Calling VSA module...\n");
|
||||
/* ECX gets SMM, EDX gets SYSMEM */
|
||||
run_vsa(MSR_GLIU0_SMM, MSR_GLIU0_SYSMEM);
|
||||
printk(BIOS_DEBUG, "... VSA module returned.\n");
|
||||
|
||||
/* Restart timer 1 */
|
||||
outb(0x56, 0x43);
|
||||
outb(0x12, 0x41);
|
||||
|
||||
/* Check that VSA is running OK */
|
||||
if (VSA_vrRead(SIGNATURE) == VSA2_SIGNATURE)
|
||||
printk(BIOS_DEBUG, "VSM: VSA2 VR signature verified.\n");
|
||||
else
|
||||
printk(BIOS_ERR, "VSM: VSA2 VR signature not valid. Install failed.\n");
|
||||
}
|
||||
#endif
|
||||
|
||||
/* interrupt_handler() is called from assembler code only,
|
||||
* so there is no use in putting the prototype into a header file.
|
||||
*/
|
||||
int __attribute__((regparm(0))) interrupt_handler(u32 intnumber,
|
||||
u32 gsfs, u32 dses,
|
||||
u32 edi, u32 esi,
|
||||
|
|
|
|||
|
|
@ -155,6 +155,105 @@ __run_optionrom = RELOCATED(.)
|
|||
popal
|
||||
ret
|
||||
|
||||
#if defined(CONFIG_GEODE_VSA) && CONFIG_GEODE_VSA
|
||||
#define VSA2_ENTRY_POINT 0x60020
|
||||
|
||||
.globl __run_vsa
|
||||
__run_vsa = RELOCATED(.)
|
||||
/* save all registers to the stack */
|
||||
pushal
|
||||
|
||||
/* Move the protected mode stack to a safe place */
|
||||
mov %esp, __stack
|
||||
|
||||
movl %esp, %ebp
|
||||
/* This function is called with regparm=0 and we have
|
||||
* to skip the 32 byte from pushal:
|
||||
*/
|
||||
movl 36(%ebp), %ecx
|
||||
movl 40(%ebp), %edx
|
||||
|
||||
/* Activate the right segment descriptor real mode. */
|
||||
ljmp $0x28, $RELOCATED(1f)
|
||||
1:
|
||||
.code16
|
||||
/* 16 bit code from here on... */
|
||||
|
||||
/* Load the segment registers w/ properly configured
|
||||
* segment descriptors. They will retain these
|
||||
* configurations (limits, writability, etc.) once
|
||||
* protected mode is turned off.
|
||||
*/
|
||||
mov $0x30, %ax
|
||||
mov %ax, %ds
|
||||
mov %ax, %es
|
||||
mov %ax, %fs
|
||||
mov %ax, %gs
|
||||
mov %ax, %ss
|
||||
|
||||
/* Turn off protection */
|
||||
movl %cr0, %eax
|
||||
andl $~PE, %eax
|
||||
movl %eax, %cr0
|
||||
|
||||
/* Now really going into real mode */
|
||||
ljmp $0, $RELOCATED(1f)
|
||||
1:
|
||||
/* Setup a stack: Put the stack at the end of page zero.
|
||||
* That way we can easily share it between real and
|
||||
* protected, since the 16-bit ESP at segment 0 will
|
||||
* work for any case. */
|
||||
mov $0x0, %ax
|
||||
mov %ax, %ss
|
||||
movl $0x1000, %eax
|
||||
movl %eax, %esp
|
||||
|
||||
/* Load our 16 bit idt */
|
||||
xor %ax, %ax
|
||||
mov %ax, %ds
|
||||
lidt __realmode_idt
|
||||
|
||||
/* Set all segments to 0x0000, ds to 0x0040 */
|
||||
mov %ax, %es
|
||||
mov %ax, %fs
|
||||
mov %ax, %gs
|
||||
mov $0x40, %ax
|
||||
mov %ax, %ds
|
||||
mov %cx, %ax // restore ax
|
||||
|
||||
/* ************************************ */
|
||||
lcall $((VSA2_ENTRY_POINT & 0xffff0000) >> 4), $(VSA2_ENTRY_POINT & 0xffff)
|
||||
/* ************************************ */
|
||||
|
||||
/* If we got here, just about done.
|
||||
* Need to get back to protected mode
|
||||
*/
|
||||
movl %cr0, %eax
|
||||
orl $PE, %eax
|
||||
movl %eax, %cr0
|
||||
|
||||
/* Now that we are in protected mode
|
||||
* jump to a 32 bit code segment.
|
||||
*/
|
||||
data32 ljmp $0x10, $RELOCATED(1f)
|
||||
1:
|
||||
.code32
|
||||
movw $0x18, %ax
|
||||
mov %ax, %ds
|
||||
mov %ax, %es
|
||||
mov %ax, %fs
|
||||
mov %ax, %gs
|
||||
mov %ax, %ss
|
||||
|
||||
/* restore proper idt */
|
||||
lidt idtarg
|
||||
|
||||
/* and exit */
|
||||
mov __stack, %esp
|
||||
popal
|
||||
ret
|
||||
#endif
|
||||
|
||||
.globl __run_interrupt
|
||||
__run_interrupt = RELOCATED(.)
|
||||
|
||||
|
|
|
|||
|
|
@ -623,6 +623,12 @@
|
|||
#define SMM_OFFSET 0x80400000 /* above 2GB */
|
||||
#define SMM_SIZE 128 /* changed SMM_SIZE from 256 KB to 128 KB */
|
||||
|
||||
|
||||
#if !defined(__ROMCC__) && !defined(ASSEMBLY)
|
||||
#if defined(__PRE_RAM__)
|
||||
void cpuRegInit(void);
|
||||
void SystemPreInit(void);
|
||||
#endif
|
||||
void cpubug(void);
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -57,46 +57,14 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
|
|||
#include "lib/generic_sdram.c"
|
||||
#include "cpu/amd/model_lx/cpureginit.c"
|
||||
#include "cpu/amd/model_lx/syspreinit.c"
|
||||
|
||||
struct msrinit {
|
||||
u32 msrnum;
|
||||
msr_t msr;
|
||||
};
|
||||
|
||||
static const struct msrinit msr_table[] =
|
||||
{
|
||||
{CPU_RCONF_DEFAULT, {.hi = 0x24fffc02,.lo = 0x1000A000}}, /* Setup access to cache under 1MB.
|
||||
* Rom Properties: Write Serialize, WriteProtect.
|
||||
* RomBase: 0xFFFC0
|
||||
* SysTop to RomBase Properties: Write Serialize, Cache Disable.
|
||||
* SysTop: 0x000A0
|
||||
* System Memory Properties: (Write Back) */
|
||||
{CPU_RCONF_A0_BF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xA0000-0xBFFFF : (Write Back) */
|
||||
{CPU_RCONF_C0_DF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xC0000-0xDFFFF : (Write Back) */
|
||||
{CPU_RCONF_E0_FF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xE0000-0xFFFFF : (Write Back) */
|
||||
|
||||
/* Setup access to memory under 1MB. Note: VGA hole at 0xA0000-0xBFFFF */
|
||||
{MSR_GLIU0_BASE1, {.hi = 0x20000000,.lo = 0x000fff80}}, // 0x00000-0x7FFFF
|
||||
{MSR_GLIU0_BASE2, {.hi = 0x20000000,.lo = 0x080fffe0}}, // 0x80000-0x9FFFF
|
||||
{MSR_GLIU0_SHADOW, {.hi = 0x2000FFFF,.lo = 0xFFFF0003}}, // 0xC0000-0xFFFFF
|
||||
{MSR_GLIU1_BASE1, {.hi = 0x20000000,.lo = 0x000fff80}}, // 0x00000-0x7FFFF
|
||||
{MSR_GLIU1_BASE2, {.hi = 0x20000000,.lo = 0x080fffe0}}, // 0x80000-0x9FFFF
|
||||
{MSR_GLIU1_SHADOW, {.hi = 0x2000FFFF,.lo = 0xFFFF0003}}, // 0xC0000-0xFFFFF
|
||||
};
|
||||
|
||||
static void msr_init(void)
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < ARRAY_SIZE(msr_table); i++)
|
||||
wrmsr(msr_table[i].msrnum, msr_table[i].msr);
|
||||
}
|
||||
#include "cpu/amd/model_lx/msrinit.c"
|
||||
|
||||
static void mb_gpio_init(void)
|
||||
{
|
||||
/* Early mainboard specific GPIO setup. */
|
||||
}
|
||||
|
||||
void cache_as_ram_main(void)
|
||||
void main(unsigned long bist)
|
||||
{
|
||||
post_code(0x01);
|
||||
|
||||
|
|
@ -117,6 +85,9 @@ void cache_as_ram_main(void)
|
|||
uart_init();
|
||||
console_init();
|
||||
|
||||
/* Halt if there was a built in self test failure */
|
||||
report_bist_failure(bist);
|
||||
|
||||
pll_reset(ManualConf);
|
||||
|
||||
cpuRegInit();
|
||||
|
|
|
|||
|
|
@ -52,46 +52,14 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
|
|||
#include "lib/generic_sdram.c"
|
||||
#include "cpu/amd/model_lx/cpureginit.c"
|
||||
#include "cpu/amd/model_lx/syspreinit.c"
|
||||
|
||||
static void msr_init(void)
|
||||
{
|
||||
msr_t msr;
|
||||
|
||||
/* Setup access to the cache for under 1MB. */
|
||||
msr.hi = 0x24fffc02;
|
||||
msr.lo = 0x1000A000; /* 0-A0000 write back */
|
||||
wrmsr(CPU_RCONF_DEFAULT, msr);
|
||||
|
||||
msr.hi = 0x0; /* write back */
|
||||
msr.lo = 0x0;
|
||||
wrmsr(CPU_RCONF_A0_BF, msr);
|
||||
wrmsr(CPU_RCONF_C0_DF, msr);
|
||||
wrmsr(CPU_RCONF_E0_FF, msr);
|
||||
|
||||
/* Setup access to the cache for under 640K. Note MC not setup yet. */
|
||||
msr.hi = 0x20000000;
|
||||
msr.lo = 0xfff80;
|
||||
wrmsr(MSR_GLIU0 + 0x20, msr);
|
||||
|
||||
msr.hi = 0x20000000;
|
||||
msr.lo = 0x80fffe0;
|
||||
wrmsr(MSR_GLIU0 + 0x21, msr);
|
||||
|
||||
msr.hi = 0x20000000;
|
||||
msr.lo = 0xfff80;
|
||||
wrmsr(MSR_GLIU1 + 0x20, msr);
|
||||
|
||||
msr.hi = 0x20000000;
|
||||
msr.lo = 0x80fffe0;
|
||||
wrmsr(MSR_GLIU1 + 0x21, msr);
|
||||
}
|
||||
#include "cpu/amd/model_lx/msrinit.c"
|
||||
|
||||
static void mb_gpio_init(void)
|
||||
{
|
||||
/* Early mainboard specific GPIO setup. */
|
||||
}
|
||||
|
||||
void cache_as_ram_main(void)
|
||||
void main(unsigned long bist)
|
||||
{
|
||||
post_code(0x01);
|
||||
|
||||
|
|
@ -116,6 +84,9 @@ void cache_as_ram_main(void)
|
|||
uart_init();
|
||||
console_init();
|
||||
|
||||
/* Halt if there was a built in self test failure */
|
||||
report_bist_failure(bist);
|
||||
|
||||
pll_reset(ManualConf);
|
||||
|
||||
cpuRegInit();
|
||||
|
|
|
|||
|
|
@ -31,7 +31,7 @@ config IRQ_SLOT_COUNT
|
|||
default 3
|
||||
depends on BOARD_ARTECGROUP_DBE61
|
||||
|
||||
config RAMBASE
|
||||
hex
|
||||
default 0x4000
|
||||
depends on BOARD_ARTECGROUP_DBE61
|
||||
#config RAMBASE
|
||||
# hex
|
||||
# default 0x4000
|
||||
## depends on BOARD_ARTECGROUP_DBE61
|
||||
|
|
|
|||
|
|
@ -69,46 +69,14 @@ static int spd_read_byte(unsigned device, unsigned address)
|
|||
#include "lib/generic_sdram.c"
|
||||
#include "cpu/amd/model_lx/cpureginit.c"
|
||||
#include "cpu/amd/model_lx/syspreinit.c"
|
||||
|
||||
struct msrinit {
|
||||
u32 msrnum;
|
||||
msr_t msr;
|
||||
};
|
||||
|
||||
static const struct msrinit msr_table[] =
|
||||
{
|
||||
{CPU_RCONF_DEFAULT, {.hi = 0x24fffc02,.lo = 0x1000A000}}, /* Setup access to cache under 1MB.
|
||||
* Rom Properties: Write Serialize, WriteProtect.
|
||||
* RomBase: 0xFFFC0
|
||||
* SysTop to RomBase Properties: Write Serialize, Cache Disable.
|
||||
* SysTop: 0x000A0
|
||||
* System Memory Properties: (Write Back) */
|
||||
{CPU_RCONF_A0_BF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xA0000-0xBFFFF : (Write Back) */
|
||||
{CPU_RCONF_C0_DF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xC0000-0xDFFFF : (Write Back) */
|
||||
{CPU_RCONF_E0_FF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xE0000-0xFFFFF : (Write Back) */
|
||||
|
||||
/* Setup access to memory under 1MB. Note: VGA hole at 0xA0000-0xBFFFF */
|
||||
{MSR_GLIU0_BASE1, {.hi = 0x20000000,.lo = 0x000fff80}}, // 0x00000-0x7FFFF
|
||||
{MSR_GLIU0_BASE2, {.hi = 0x20000000,.lo = 0x080fffe0}}, // 0x80000-0x9FFFF
|
||||
{MSR_GLIU0_SHADOW, {.hi = 0x2000FFFF,.lo = 0xFFFF0003}}, // 0xC0000-0xFFFFF
|
||||
{MSR_GLIU1_BASE1, {.hi = 0x20000000,.lo = 0x000fff80}}, // 0x00000-0x7FFFF
|
||||
{MSR_GLIU1_BASE2, {.hi = 0x20000000,.lo = 0x080fffe0}}, // 0x80000-0x9FFFF
|
||||
{MSR_GLIU1_SHADOW, {.hi = 0x2000FFFF,.lo = 0xFFFF0003}}, // 0xC0000-0xFFFFF
|
||||
};
|
||||
|
||||
static void msr_init(void)
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < ARRAY_SIZE(msr_table); i++)
|
||||
wrmsr(msr_table[i].msrnum, msr_table[i].msr);
|
||||
}
|
||||
#include "cpu/amd/model_lx/msrinit.c"
|
||||
|
||||
static void mb_gpio_init(void)
|
||||
{
|
||||
/* Early mainboard specific GPIO setup */
|
||||
}
|
||||
|
||||
void cache_as_ram_main(void)
|
||||
void main(unsigned long bist)
|
||||
{
|
||||
post_code(0x01);
|
||||
|
||||
|
|
@ -137,6 +105,9 @@ void cache_as_ram_main(void)
|
|||
uart_init();
|
||||
console_init();
|
||||
|
||||
/* Halt if there was a built in self test failure */
|
||||
report_bist_failure(bist);
|
||||
|
||||
pll_reset(ManualConf);
|
||||
|
||||
cpuRegInit();
|
||||
|
|
@ -144,8 +115,7 @@ void cache_as_ram_main(void)
|
|||
sdram_initialize(1, memctrl);
|
||||
|
||||
/* Dump memory configuratation */
|
||||
/*{
|
||||
msr_t msr;
|
||||
#if 0
|
||||
msr = rdmsr(MC_CF07_DATA);
|
||||
print_debug("MC_CF07_DATA: ");
|
||||
print_debug_hex32(MC_CF07_DATA);
|
||||
|
|
@ -173,9 +143,10 @@ void cache_as_ram_main(void)
|
|||
print_debug_hex32(msr.lo);
|
||||
msr = rdmsr(MC_CF8F_DATA);
|
||||
print_debug(" \n");
|
||||
}*/
|
||||
#endif
|
||||
|
||||
/* Check memory. */
|
||||
/* ram_check(0x00000000, 640 * 1024); */
|
||||
// ram_check(0x00000000, 640 * 1024);
|
||||
// ram_check(1024 * 1024, 2 * 1024 * 1024);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -35,30 +35,14 @@ static inline int spd_read_byte(unsigned device, unsigned address)
|
|||
#include "lib/generic_sdram.c"
|
||||
#include "cpu/amd/model_lx/cpureginit.c"
|
||||
#include "cpu/amd/model_lx/syspreinit.c"
|
||||
|
||||
static void msr_init(void)
|
||||
{
|
||||
msr_t msr;
|
||||
/* Setup access to the MC for under 1MB. Note MC not setup yet. */
|
||||
msr.hi = 0x24fffc02;
|
||||
msr.lo = 0x10010000;
|
||||
wrmsr(CPU_RCONF_DEFAULT, msr);
|
||||
|
||||
msr.hi = 0x20000000;
|
||||
msr.lo = 0xfff00;
|
||||
wrmsr(MSR_GLIU0 + 0x20, msr);
|
||||
|
||||
msr.hi = 0x20000000;
|
||||
msr.lo = 0xfff00;
|
||||
wrmsr(MSR_GLIU1 + 0x20, msr);
|
||||
}
|
||||
#include "cpu/amd/model_lx/msrinit.c"
|
||||
|
||||
static void mb_gpio_init(void)
|
||||
{
|
||||
/* Early mainboard specific GPIO setup */
|
||||
}
|
||||
|
||||
void cache_as_ram_main(void)
|
||||
void main(unsigned long bist)
|
||||
{
|
||||
post_code(0x01);
|
||||
|
||||
|
|
@ -81,6 +65,9 @@ void cache_as_ram_main(void)
|
|||
uart_init();
|
||||
console_init();
|
||||
|
||||
/* Halt if there was a built in self test failure */
|
||||
report_bist_failure(bist);
|
||||
|
||||
pll_reset(ManualConf);
|
||||
|
||||
cpuRegInit();
|
||||
|
|
|
|||
|
|
@ -60,46 +60,14 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
|
|||
#include "lib/generic_sdram.c"
|
||||
#include "cpu/amd/model_lx/cpureginit.c"
|
||||
#include "cpu/amd/model_lx/syspreinit.c"
|
||||
|
||||
static void msr_init(void)
|
||||
{
|
||||
msr_t msr;
|
||||
|
||||
/* Setup access to the cache for under 1MB. */
|
||||
msr.hi = 0x24fffc02;
|
||||
msr.lo = 0x1000A000; /* 0-A0000 write back */
|
||||
wrmsr(CPU_RCONF_DEFAULT, msr);
|
||||
|
||||
msr.hi = 0x0; /* Write back */
|
||||
msr.lo = 0x0;
|
||||
wrmsr(CPU_RCONF_A0_BF, msr);
|
||||
wrmsr(CPU_RCONF_C0_DF, msr);
|
||||
wrmsr(CPU_RCONF_E0_FF, msr);
|
||||
|
||||
/* Setup access to the cache for under 640K. Note MC not setup yet. */
|
||||
msr.hi = 0x20000000;
|
||||
msr.lo = 0xfff80;
|
||||
wrmsr(MSR_GLIU0 + 0x20, msr);
|
||||
|
||||
msr.hi = 0x20000000;
|
||||
msr.lo = 0x80fffe0;
|
||||
wrmsr(MSR_GLIU0 + 0x21, msr);
|
||||
|
||||
msr.hi = 0x20000000;
|
||||
msr.lo = 0xfff80;
|
||||
wrmsr(MSR_GLIU1 + 0x20, msr);
|
||||
|
||||
msr.hi = 0x20000000;
|
||||
msr.lo = 0x80fffe0;
|
||||
wrmsr(MSR_GLIU1 + 0x21, msr);
|
||||
}
|
||||
#include "cpu/amd/model_lx/msrinit.c"
|
||||
|
||||
static void mb_gpio_init(void)
|
||||
{
|
||||
/* Early mainboard specific GPIO setup. */
|
||||
}
|
||||
|
||||
void cache_as_ram_main(void)
|
||||
void main(unsigned long bist)
|
||||
{
|
||||
post_code(0x01);
|
||||
|
||||
|
|
@ -120,6 +88,9 @@ void cache_as_ram_main(void)
|
|||
uart_init();
|
||||
console_init();
|
||||
|
||||
/* Halt if there was a built in self test failure */
|
||||
report_bist_failure(bist);
|
||||
|
||||
pll_reset(ManualConf);
|
||||
|
||||
cpuRegInit();
|
||||
|
|
|
|||
|
|
@ -60,39 +60,7 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
|
|||
#include "lib/generic_sdram.c"
|
||||
#include "cpu/amd/model_lx/cpureginit.c"
|
||||
#include "cpu/amd/model_lx/syspreinit.c"
|
||||
|
||||
static void msr_init(void)
|
||||
{
|
||||
msr_t msr;
|
||||
|
||||
/* Setup access to the cache for under 1MB. */
|
||||
msr.hi = 0x24fffc02;
|
||||
msr.lo = 0x1000A000; /* 0-A0000 write back */
|
||||
wrmsr(CPU_RCONF_DEFAULT, msr);
|
||||
|
||||
msr.hi = 0x0; /* Write back */
|
||||
msr.lo = 0x0;
|
||||
wrmsr(CPU_RCONF_A0_BF, msr);
|
||||
wrmsr(CPU_RCONF_C0_DF, msr);
|
||||
wrmsr(CPU_RCONF_E0_FF, msr);
|
||||
|
||||
/* Setup access to the cache for under 640K. Note MC not setup yet. */
|
||||
msr.hi = 0x20000000;
|
||||
msr.lo = 0xfff80;
|
||||
wrmsr(MSR_GLIU0 + 0x20, msr);
|
||||
|
||||
msr.hi = 0x20000000;
|
||||
msr.lo = 0x80fffe0;
|
||||
wrmsr(MSR_GLIU0 + 0x21, msr);
|
||||
|
||||
msr.hi = 0x20000000;
|
||||
msr.lo = 0xfff80;
|
||||
wrmsr(MSR_GLIU1 + 0x20, msr);
|
||||
|
||||
msr.hi = 0x20000000;
|
||||
msr.lo = 0x80fffe0;
|
||||
wrmsr(MSR_GLIU1 + 0x21, msr);
|
||||
}
|
||||
#include "cpu/amd/model_lx/msrinit.c"
|
||||
|
||||
static const u16 sio_init_table[] = { // hi=data, lo=index
|
||||
0x0707, // select LDN 7 (GPIO, SPI, watchdog, ...)
|
||||
|
|
@ -128,7 +96,7 @@ static void mb_gpio_init(void)
|
|||
it8712f_exit_conf();
|
||||
}
|
||||
|
||||
void cache_as_ram_main(void)
|
||||
void main(unsigned long bist)
|
||||
{
|
||||
post_code(0x01);
|
||||
|
||||
|
|
@ -150,6 +118,9 @@ void cache_as_ram_main(void)
|
|||
uart_init();
|
||||
console_init();
|
||||
|
||||
/* Halt if there was a built in self test failure */
|
||||
report_bist_failure(bist);
|
||||
|
||||
pll_reset(ManualConf);
|
||||
|
||||
cpuRegInit();
|
||||
|
|
|
|||
|
|
@ -122,39 +122,7 @@ static int smc_send_config(unsigned char config_data)
|
|||
#include "lib/generic_sdram.c"
|
||||
#include "cpu/amd/model_lx/cpureginit.c"
|
||||
#include "cpu/amd/model_lx/syspreinit.c"
|
||||
|
||||
static void msr_init(void)
|
||||
{
|
||||
msr_t msr;
|
||||
|
||||
/* Setup access to the cache for under 1MB. */
|
||||
msr.hi = 0x24fffc02;
|
||||
msr.lo = 0x1000A000; /* 0-A0000 write back */
|
||||
wrmsr(CPU_RCONF_DEFAULT, msr);
|
||||
|
||||
msr.hi = 0x0; /* Write back */
|
||||
msr.lo = 0x0;
|
||||
wrmsr(CPU_RCONF_A0_BF, msr);
|
||||
wrmsr(CPU_RCONF_C0_DF, msr);
|
||||
wrmsr(CPU_RCONF_E0_FF, msr);
|
||||
|
||||
/* Setup access to the cache for under 640K. Note MC not setup yet. */
|
||||
msr.hi = 0x20000000;
|
||||
msr.lo = 0xfff80;
|
||||
wrmsr(MSR_GLIU0 + 0x20, msr);
|
||||
|
||||
msr.hi = 0x20000000;
|
||||
msr.lo = 0x80fffe0;
|
||||
wrmsr(MSR_GLIU0 + 0x21, msr);
|
||||
|
||||
msr.hi = 0x20000000;
|
||||
msr.lo = 0xfff80;
|
||||
wrmsr(MSR_GLIU1 + 0x20, msr);
|
||||
|
||||
msr.hi = 0x20000000;
|
||||
msr.lo = 0x80fffe0;
|
||||
wrmsr(MSR_GLIU1 + 0x21, msr);
|
||||
}
|
||||
#include "cpu/amd/model_lx/msrinit.c"
|
||||
|
||||
static const u16 sio_init_table[] = { // hi=data, lo=index
|
||||
0x0707, // select LDN 7 (GPIO, SPI, watchdog, ...)
|
||||
|
|
@ -189,7 +157,7 @@ static void mb_gpio_init(void)
|
|||
it8712f_exit_conf();
|
||||
}
|
||||
|
||||
void cache_as_ram_main(void)
|
||||
void main(unsigned long bist)
|
||||
{
|
||||
int err;
|
||||
post_code(0x01);
|
||||
|
|
@ -212,6 +180,9 @@ void cache_as_ram_main(void)
|
|||
uart_init();
|
||||
console_init();
|
||||
|
||||
/* Halt if there was a built in self test failure */
|
||||
report_bist_failure(bist);
|
||||
|
||||
pll_reset(ManualConf);
|
||||
|
||||
cpuRegInit();
|
||||
|
|
|
|||
|
|
@ -115,31 +115,14 @@ static u8 spd_read_byte(u8 device, u8 address)
|
|||
#include "lib/generic_sdram.c"
|
||||
#include "cpu/amd/model_lx/cpureginit.c"
|
||||
#include "cpu/amd/model_lx/syspreinit.c"
|
||||
|
||||
static void msr_init(void)
|
||||
{
|
||||
msr_t msr;
|
||||
|
||||
/* Setup access to the MC for under 1MB. Note MC not setup yet. */
|
||||
msr.hi = 0x24fffc02;
|
||||
msr.lo = 0x10010000;
|
||||
wrmsr(CPU_RCONF_DEFAULT, msr);
|
||||
|
||||
msr.hi = 0x20000000;
|
||||
msr.lo = 0xfff00;
|
||||
wrmsr(MSR_GLIU0 + 0x20, msr);
|
||||
|
||||
msr.hi = 0x20000000;
|
||||
msr.lo = 0xfff00;
|
||||
wrmsr(MSR_GLIU1 + 0x20, msr);
|
||||
}
|
||||
#include "cpu/amd/model_lx/msrinit.c"
|
||||
|
||||
/** Early mainboard specific GPIO setup. */
|
||||
static void mb_gpio_init(void)
|
||||
{
|
||||
}
|
||||
|
||||
void cache_as_ram_main(void)
|
||||
void main(unsigned long bist)
|
||||
{
|
||||
static const struct mem_controller memctrl[] = {
|
||||
{.channel0 = {0x50}},
|
||||
|
|
@ -161,6 +144,9 @@ void cache_as_ram_main(void)
|
|||
uart_init();
|
||||
console_init();
|
||||
|
||||
/* Halt if there was a built in self test failure */
|
||||
report_bist_failure(bist);
|
||||
|
||||
pll_reset(ManualConf);
|
||||
|
||||
cpuRegInit();
|
||||
|
|
|
|||
|
|
@ -57,46 +57,14 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
|
|||
#include "lib/generic_sdram.c"
|
||||
#include "cpu/amd/model_lx/cpureginit.c"
|
||||
#include "cpu/amd/model_lx/syspreinit.c"
|
||||
|
||||
struct msrinit {
|
||||
u32 msrnum;
|
||||
msr_t msr;
|
||||
};
|
||||
|
||||
static const struct msrinit msr_table[] =
|
||||
{
|
||||
{CPU_RCONF_DEFAULT, {.hi = 0x24fffc02,.lo = 0x1000A000}}, /* Setup access to cache under 1MB.
|
||||
* Rom Properties: Write Serialize, WriteProtect.
|
||||
* RomBase: 0xFFFC0
|
||||
* SysTop to RomBase Properties: Write Serialize, Cache Disable.
|
||||
* SysTop: 0x000A0
|
||||
* System Memory Properties: (Write Back) */
|
||||
{CPU_RCONF_A0_BF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xA0000-0xBFFFF : (Write Back) */
|
||||
{CPU_RCONF_C0_DF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xC0000-0xDFFFF : (Write Back) */
|
||||
{CPU_RCONF_E0_FF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xE0000-0xFFFFF : (Write Back) */
|
||||
|
||||
/* Setup access to memory under 1MB. Note: VGA hole at 0xA0000-0xBFFFF */
|
||||
{MSR_GLIU0_BASE1, {.hi = 0x20000000,.lo = 0x000fff80}}, // 0x00000-0x7FFFF
|
||||
{MSR_GLIU0_BASE2, {.hi = 0x20000000,.lo = 0x080fffe0}}, // 0x80000-0x9FFFF
|
||||
{MSR_GLIU0_SHADOW, {.hi = 0x2000FFFF,.lo = 0xFFFF0003}}, // 0xC0000-0xFFFFF
|
||||
{MSR_GLIU1_BASE1, {.hi = 0x20000000,.lo = 0x000fff80}}, // 0x00000-0x7FFFF
|
||||
{MSR_GLIU1_BASE2, {.hi = 0x20000000,.lo = 0x080fffe0}}, // 0x80000-0x9FFFF
|
||||
{MSR_GLIU1_SHADOW, {.hi = 0x2000FFFF,.lo = 0xFFFF0003}}, // 0xC0000-0xFFFFF
|
||||
};
|
||||
|
||||
static void msr_init(void)
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < ARRAY_SIZE(msr_table); i++)
|
||||
wrmsr(msr_table[i].msrnum, msr_table[i].msr);
|
||||
}
|
||||
#include "cpu/amd/model_lx/msrinit.c"
|
||||
|
||||
static void mb_gpio_init(void)
|
||||
{
|
||||
/* Early mainboard specific GPIO setup. */
|
||||
}
|
||||
|
||||
void cache_as_ram_main(void)
|
||||
void main(unsigned long bist)
|
||||
{
|
||||
post_code(0x01);
|
||||
|
||||
|
|
@ -118,6 +86,9 @@ void cache_as_ram_main(void)
|
|||
uart_init();
|
||||
console_init();
|
||||
|
||||
/* Halt if there was a built in self test failure */
|
||||
report_bist_failure(bist);
|
||||
|
||||
pll_reset(ManualConf);
|
||||
|
||||
cpuRegInit();
|
||||
|
|
|
|||
|
|
@ -19,4 +19,6 @@
|
|||
|
||||
config NORTHBRIDGE_AMD_GX2
|
||||
bool
|
||||
# for VSM:
|
||||
select PCI_OPTION_ROM_RUN_REALMODE
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
config NORTHBRIDGE_AMD_LX
|
||||
bool
|
||||
select HAVE_HIGH_TABLES
|
||||
# for VSM:
|
||||
select PCI_OPTION_ROM_RUN_REALMODE
|
||||
|
||||
config VIDEO_MB
|
||||
int
|
||||
|
|
|
|||
|
|
@ -74,11 +74,8 @@
|
|||
#define IOD_BM(msr, pdid1, bizarro, ibase, imask) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(ibase>>12), .lo=(ibase<<20)|imask}}
|
||||
#define IOD_SC(msr, pdid1, bizarro, en, wen, ren, ibase) {msr, {.hi=(pdid1<<29)|(bizarro<<28), .lo=(en<<24)|(wen<<21)|(ren<<20)|(ibase<<3)}}
|
||||
|
||||
extern void graphics_init(void);
|
||||
extern void cpubug(void);
|
||||
extern void chipsetinit(void);
|
||||
|
||||
void setup_realmode_idt(void);
|
||||
void print_conf(void);
|
||||
void graphics_init(void);
|
||||
void do_vsmbios(void);
|
||||
|
||||
struct msr_defaults {
|
||||
|
|
@ -319,7 +316,7 @@ static void northbridge_init(device_t dev)
|
|||
//printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MSR_GLIU1_SHADOW, msr.hi, msr.lo);
|
||||
}
|
||||
|
||||
void northbridge_set_resources(struct device *dev)
|
||||
static void northbridge_set_resources(struct device *dev)
|
||||
{
|
||||
struct resource *resource, *last;
|
||||
unsigned link;
|
||||
|
|
@ -426,7 +423,6 @@ static void pci_domain_set_resources(device_t dev)
|
|||
|
||||
static void pci_domain_enable(device_t dev)
|
||||
{
|
||||
|
||||
printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__);
|
||||
|
||||
// do this here for now -- this chip really breaks our device model
|
||||
|
|
@ -434,14 +430,10 @@ static void pci_domain_enable(device_t dev)
|
|||
cpubug();
|
||||
chipsetinit();
|
||||
|
||||
setup_realmode_idt();
|
||||
|
||||
printk(BIOS_DEBUG, "Before VSA:\n");
|
||||
// print_conf();
|
||||
|
||||
do_vsmbios(); // do the magic stuff here, so prepare your tambourine ;)
|
||||
|
||||
printk(BIOS_DEBUG, "After VSA:\n");
|
||||
// print_conf();
|
||||
|
||||
graphics_init();
|
||||
|
|
|
|||
|
|
@ -464,4 +464,13 @@
|
|||
#define FLASH_IO_128B 0x0000FF80
|
||||
#define FLASH_IO_256B 0x0000FF00
|
||||
|
||||
#if !defined(ASSEMBLY) && !defined(__ROMCC__)
|
||||
#if defined(__PRE_RAM__)
|
||||
void cs5536_setup_onchipuart(int uart);
|
||||
void cs5536_disable_internal_uart(void);
|
||||
#else
|
||||
void chipsetinit(void);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#endif /* _CS5536_H */
|
||||
|
|
|
|||
|
|
@ -121,7 +121,7 @@ static void cs5536_setup_gpio(void)
|
|||
outl(val, GPIO_IO_BASE + GPIOL_INPUT_ENABLE);
|
||||
}
|
||||
|
||||
static void cs5536_disable_internal_uart(void)
|
||||
void cs5536_disable_internal_uart(void)
|
||||
{
|
||||
msr_t msr;
|
||||
/* The UARTs default to enabled.
|
||||
|
|
|
|||
Loading…
Reference in New Issue