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mb/cannonlake: Remove SmbusEnable from devicetree 

Remove the SmbusEnable parameter from all Cannon Lake mainboards.
Instead this will be determined by the enable state of the SMBUS
PCI device.

Change-Id: I7ece6768da4c517747af12a07012583575816ae1
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29551
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Duncan Laurie 2018-11-08 15:46:16 -07:00 committed by Duncan Laurie
parent 6efa5c3846
commit 98456f4ee6
7 changed files with 0 additions and 7 deletions
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1
src/mainboard/google/zoombini/variants/baseboard/devicetree.cb
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@ -20,7 +20,6 @@ chip soc/intel/cannonlake
# FSP configuration
register "SaGv" = "3"
register "SmbusEnable" = "1"
register "ScsEmmcHs400Enabled" = "1"
# Intel Common SoC Config

1
src/mainboard/google/zoombini/variants/meowth/devicetree.cb
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@ -29,7 +29,6 @@ chip soc/intel/cannonlake
# FSP configuration
register "SaGv" = "SaGv_Enabled"
register "SmbusEnable" = "1"
register "ScsEmmcHs400Enabled" = "1"
# Intel Common SoC Config

1
src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
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@ -6,7 +6,6 @@ chip soc/intel/cannonlake
# FSP configuration
register "SaGv" = "3"
register "SmbusEnable" = "1"
register "ScsEmmcHs400Enabled" = "1"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"

1
src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
View File

@ -6,7 +6,6 @@ chip soc/intel/cannonlake
# FSP configuration
register "SaGv" = "3"
register "SmbusEnable" = "1"
register "ScsEmmcHs400Enabled" = "1"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"

1
src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb
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@ -7,7 +7,6 @@ chip soc/intel/cannonlake
# FSP configuration
register "SaGv" = "3"
register "RMT" = "1"
register "SmbusEnable" = "1"
register "ScsEmmcHs400Enabled" = "1"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC5)"

1
src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb
View File

@ -7,7 +7,6 @@ chip soc/intel/cannonlake
# FSP configuration
register "SaGv" = "3"
register "RMT" = "1"
register "SmbusEnable" = "1"
register "ScsEmmcHs400Enabled" = "1"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC4)"

1
src/mainboard/intel/coffeelake_rvp/variants/cfl_u/devicetree.cb
View File

@ -6,7 +6,6 @@ chip soc/intel/cannonlake
# FSP configuration
register "SaGv" = "3"
register "SmbusEnable" = "1"
register "ScsEmmcHs400Enabled" = "1"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"