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soc/intel: Replace `SA_PCIEX_LENGTH` Kconfig options 

Use the existing `MMCONF_BUS_NUMBER` and `MMCONF_LENGTH` symbols.

Change-Id: I88dcc0d5845198f668c6604c45fd869617168231
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Angel Pons 2021-01-29 11:35:16 +01:00
parent 90be7544e4
commit 9849488da1
13 changed files with 19 additions and 33 deletions
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2
src/security/intel/stm/StmPlatformResource.c
View File

@ -98,7 +98,7 @@ MSR_TABLE_ENTRY msr_table[] = {
static void fixup_pciex_resource(void)
{
// Find max bus number and PCIEX length
rsc_pcie_mmio.length = CONFIG_SA_PCIEX_LENGTH; // 0x10000000;// 256 MB
rsc_pcie_mmio.length = CONFIG_MMCONF_LENGTH; // 0x10000000;// 256 MB
rsc_pcie_mmio.base = CONFIG_MMCONF_BASE_ADDRESS;
}

2
src/soc/intel/alderlake/systemagent.c
View File

@ -21,7 +21,7 @@
void soc_add_fixed_mmio_resources(struct device *dev, int *index)
{
static const struct sa_mmio_descriptor soc_fixed_resources[] = {
{ PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH,
{ PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH,
"PCIEXBAR" },
{ MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
{ DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" },

2
src/soc/intel/apollolake/systemagent.c
View File

@ -18,7 +18,7 @@
void soc_add_fixed_mmio_resources(struct device *dev, int *index)
{
static const struct sa_mmio_descriptor soc_fixed_resources[] = {
{ PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH,
{ PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH,
"PCIEXBAR" },
{ MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
};

2
src/soc/intel/cannonlake/systemagent.c
View File

@ -20,7 +20,7 @@
void soc_add_fixed_mmio_resources(struct device *dev, int *index)
{
static const struct sa_mmio_descriptor soc_fixed_resources[] = {
{ PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH,
{ PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH,
"PCIEXBAR" },
{ MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
{ DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" },

2
src/soc/intel/common/block/acpi/acpi.c
View File

@ -29,7 +29,7 @@ __attribute__((weak)) unsigned long acpi_fill_mcfg(unsigned long current)
/* PCI Segment Group 0, Start Bus Number 0, End Bus Number is 255 */
current += acpi_create_mcfg_mmconfig((void *)current,
CONFIG_MMCONF_BASE_ADDRESS, 0, 0,
(CONFIG_SA_PCIEX_LENGTH >> 20) - 1);
CONFIG_MMCONF_BUS_NUMBER - 1);
return current;
}

19
src/soc/intel/common/block/systemagent/Kconfig
View File

@ -8,23 +8,8 @@ if SOC_INTEL_COMMON_BLOCK_SA
config MMCONF_BASE_ADDRESS
default 0xe0000000
config SA_PCIEX_LENGTH
hex
default 0x10000000 if (PCIEX_LENGTH_256MB)
default 0x8000000 if (PCIEX_LENGTH_128MB)
default 0x4000000 if (PCIEX_LENGTH_64MB)
default 0x10000000
help
This option allows you to select length of PCIEX region.
config PCIEX_LENGTH_256MB
bool
config PCIEX_LENGTH_128MB
bool
config PCIEX_LENGTH_64MB
bool
config MMCONF_BUS_NUMBER
default 256
config SA_ENABLE_IMR
bool

11
src/soc/intel/common/block/systemagent/systemagent_early.c
View File

@ -2,6 +2,7 @@
#define __SIMPLE_DEVICE__
#include <assert.h>
#include <device/mmio.h>
#include <device/pci_ops.h>
#include <device/device.h>
@ -28,18 +29,18 @@ void bootblock_systemagent_early_init(void)
pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR + 4, reg);
/* Get PCI Express Region Length */
switch (CONFIG_SA_PCIEX_LENGTH) {
case 256 * MiB:
switch (CONFIG_MMCONF_BUS_NUMBER) {
case 256:
pciexbar_length = PCIEXBAR_LENGTH_256MB;
break;
case 128 * MiB:
case 128:
pciexbar_length = PCIEXBAR_LENGTH_128MB;
break;
case 64 * MiB:
case 64:
pciexbar_length = PCIEXBAR_LENGTH_64MB;
break;
default:
pciexbar_length = PCIEXBAR_LENGTH_256MB;
dead_code();
}
reg = CONFIG_MMCONF_BASE_ADDRESS | (pciexbar_length << 1)
| PCIEXBAR_PCIEXBAREN;

2
src/soc/intel/elkhartlake/systemagent.c
View File

@ -19,7 +19,7 @@
void soc_add_fixed_mmio_resources(struct device *dev, int *index)
{
static const struct sa_mmio_descriptor soc_fixed_resources[] = {
{ PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH,
{ PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH,
"PCIEXBAR" },
{ MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
{ DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" },

2
src/soc/intel/icelake/systemagent.c
View File

@ -15,7 +15,7 @@
void soc_add_fixed_mmio_resources(struct device *dev, int *index)
{
static const struct sa_mmio_descriptor soc_fixed_resources[] = {
{ PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH,
{ PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH,
"PCIEXBAR" },
{ MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
{ DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" },

2
src/soc/intel/jasperlake/systemagent.c
View File

@ -19,7 +19,7 @@
void soc_add_fixed_mmio_resources(struct device *dev, int *index)
{
static const struct sa_mmio_descriptor soc_fixed_resources[] = {
{ PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH,
{ PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH,
"PCIEXBAR" },
{ MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
{ DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" },

2
src/soc/intel/skylake/acpi.c
View File

@ -184,7 +184,7 @@ unsigned long acpi_fill_mcfg(unsigned long current)
{
current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current,
CONFIG_MMCONF_BASE_ADDRESS, 0, 0,
(CONFIG_SA_PCIEX_LENGTH >> 20) - 1);
CONFIG_MMCONF_BUS_NUMBER - 1);
return current;
}

2
src/soc/intel/skylake/systemagent.c
View File

@ -31,7 +31,7 @@ void soc_add_fixed_mmio_resources(struct device *dev, int *index)
struct device *const igd_dev = pcidev_path_on_root(SA_DEVFN_IGD);
static const struct sa_mmio_descriptor soc_fixed_resources[] = {
{ PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH,
{ PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH,
"PCIEXBAR" },
{ MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
{ DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" },

2
src/soc/intel/tigerlake/systemagent.c
View File

@ -27,7 +27,7 @@
void soc_add_fixed_mmio_resources(struct device *dev, int *index)
{
static const struct sa_mmio_descriptor soc_fixed_resources[] = {
{ PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH,
{ PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH,
"PCIEXBAR" },
{ MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
{ DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" },