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soc/intel/xeon_sp/skx/: Clean up soc_util.c 

Remove unused c_util.c helper functions and clean up soc_util.h in
preparation for merging common code with cpx/.

Change-Id: Iff825f64b665aadcf8eac8a404191c0b74f92abd
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46094
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Marc Jones 2020-10-05 17:11:13 -06:00 committed by Marc Jones
parent 97321db21d
commit 985d956833
2 changed files with 12 additions and 80 deletions
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30
src/soc/intel/xeon_sp/skx/include/soc/soc_util.h
View File

@ -5,34 +5,26 @@
#include <hob_iiouds.h> #include <hob_iiouds.h>
#include <hob_memmap.h> #include <hob_memmap.h>
#include <acpi/acpi.h>
#include <soc/util.h>
struct iiostack_resource { struct iiostack_resource {
uint8_t no_of_stacks; uint8_t no_of_stacks;
STACK_RES res[CONFIG_MAX_SOCKET * MAX_IIO_STACK]; STACK_RES res[CONFIG_MAX_SOCKET * MAX_IIO_STACK];
}; };
uintptr_t get_tolm(uint32_t bus);
void get_tseg_base_lim(uint32_t bus, uint32_t *base, uint32_t *limit);
uintptr_t get_cha_mmcfg_base(uint32_t bus);
uint32_t top_of_32bit_ram(void); // Top of 32bit usable memory
uint32_t pci_read_mmio_reg(int bus, uint32_t dev, uint32_t func, int offset);
uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack);
void get_iiostack_info(struct iiostack_resource *info); void get_iiostack_info(struct iiostack_resource *info);
int get_threads_per_package(void);
int get_platform_thread_count(void);
void get_core_thread_bits(uint32_t *core_bits, uint32_t *thread_bits);
void get_cpu_info_from_apicid(uint32_t apicid, uint32_t core_bits,
uint32_t thread_bits, uint8_t *package, uint8_t *core, uint8_t *thread);
const struct SystemMemoryMapHob *get_system_memory_map(void);
void xeonsp_init_cpu_config(void); void xeonsp_init_cpu_config(void);
void set_bios_init_completion(void);
void config_reset_cpl3_csrs(void); void config_reset_cpl3_csrs(void);
void get_core_thread_bits(uint32_t *core_bits, uint32_t *thread_bits);
void get_cpu_info_from_apicid(uint32_t apicid, uint32_t core_bits, uint32_t thread_bits,
uint8_t *package, uint8_t *core, uint8_t *thread);
int get_platform_thread_count(void);
int get_threads_per_package(void);
const struct SystemMemoryMapHob *get_system_memory_map(void);
void set_bios_init_completion(void);
#endif /* _SOC_UTIL_H_ */ #endif /* _SOC_UTIL_H_ */

62
src/soc/intel/xeon_sp/skx/soc_util.c
View File

@ -17,61 +17,6 @@
#include <soc/util.h> #include <soc/util.h>
#include <timer.h> #include <timer.h>
/*
* Get TOLM CSR B0:D5:F0:Offset_d0h
*/
uintptr_t get_tolm(uint32_t bus)
{
uint32_t w = pci_io_read_config32(PCI_DEV(bus, VTD_DEV, VTD_FUNC),
VTD_TOLM_CSR);
uintptr_t addr = w & 0xfc000000;
printk(BIOS_DEBUG, "VTD_TOLM_CSR 0x%x, addr: 0x%lx\n", w, addr);
return addr;
}
void get_tseg_base_lim(uint32_t bus, uint32_t *base, uint32_t *limit)
{
uint32_t w1 = pci_io_read_config32(PCI_DEV(bus, VTD_DEV, VTD_FUNC),
VTD_TSEG_BASE_CSR);
uint32_t wh = pci_io_read_config32(PCI_DEV(bus, VTD_DEV, VTD_FUNC),
VTD_TSEG_LIMIT_CSR);
*base = w1 & 0xfff00000;
*limit = wh & 0xfff00000;
}
/*
* Get MMCFG CSR B1:D29:F1:Offset_C0h
*/
uintptr_t get_cha_mmcfg_base(uint32_t bus)
{
uint32_t wl = pci_io_read_config32(PCI_DEV(bus, CHA_UTIL_ALL_DEV,
CHA_UTIL_ALL_FUNC), CHA_UTIL_ALL_MMCFG_CSR);
uint32_t wh = pci_io_read_config32(PCI_DEV(bus, CHA_UTIL_ALL_DEV,
CHA_UTIL_ALL_FUNC), CHA_UTIL_ALL_MMCFG_CSR + 4);
uintptr_t addr = ((((wh & 0x3fff) << 6) | ((wl >> 26) & 0x3f)) << 26);
printk(BIOS_DEBUG, "CHA_UTIL_ALL_MMCFG_CSR wl: 0x%x, wh: 0x%x, addr: 0x%lx\n",
wl, wh, addr);
return addr;
}
uint32_t top_of_32bit_ram(void)
{
uintptr_t mmcfg, tolm;
uint32_t bus0 = 0, bus1 = 0;
uint32_t base = 0, limit = 0;
get_cpubusnos(&bus0, &bus1, NULL, NULL);
mmcfg = get_cha_mmcfg_base(bus1);
tolm = get_tolm(bus0);
printk(BIOS_DEBUG, "bus0: 0x%x, bus1: 0x%x, mmcfg: 0x%lx, tolm: 0x%lx\n",
bus0, bus1, mmcfg, tolm);
get_tseg_base_lim(bus0, &base, &limit);
printk(BIOS_DEBUG, "tseg base: 0x%x, limit: 0x%x\n", base, limit);
/* We will use TSEG base as the top of DRAM */
return base;
}
/* /*
* +-------------------------+ TOLM * +-------------------------+ TOLM
@ -101,12 +46,7 @@ uint32_t top_of_32bit_ram(void)
* +-------------------------+ * +-------------------------+
*/ */
uint32_t pci_read_mmio_reg(int bus, uint32_t dev, uint32_t func, int offset) static uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack)
{
return pci_mmio_read_config32(PCI_DEV(bus, dev, func), offset);
}
uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack)
{ {
size_t hob_size; size_t hob_size;
const IIO_UDS *hob; const IIO_UDS *hob;