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soc/amd/picasso/data_fabric: factor out common MMIO register defines 

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I663a73308d33f48c6b945007f3eaac84d4712f59
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50639
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Held 2021-02-13 20:47:04 +01:00
parent 602f93ed52
commit 985f3e05e3
2 changed files with 17 additions and 13 deletions
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15
src/soc/amd/common/block/include/amdblocks/data_fabric.h
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@ -10,6 +10,21 @@
#define BROADCAST_FABRIC_ID 0xff #define BROADCAST_FABRIC_ID 0xff
/* D18F0 - Fabric Configuration registers */
#define D18F0_MMIO_BASE0 0x200
#define D18F0_MMIO_LIMIT0 0x204
#define D18F0_MMIO_SHIFT 16
#define D18F0_MMIO_CTRL0 0x208
#define MMIO_NP BIT(12)
#define MMIO_DST_FABRIC_ID_SHIFT 4
#define MMIO_WE BIT(1)
#define MMIO_RE BIT(0)
/* The number of data fabric MMIO registers is SoC-specific */
#define NB_MMIO_BASE(reg) ((reg) * 4 * sizeof(uint32_t) + D18F0_MMIO_BASE0)
#define NB_MMIO_LIMIT(reg) ((reg) * 4 * sizeof(uint32_t) + D18F0_MMIO_LIMIT0)
#define NB_MMIO_CONTROL(reg) ((reg) * 4 * sizeof(uint32_t) + D18F0_MMIO_CTRL0)
uint32_t data_fabric_read32(uint8_t function, uint16_t reg, uint8_t instance_id); uint32_t data_fabric_read32(uint8_t function, uint16_t reg, uint8_t instance_id);
void data_fabric_write32(uint8_t function, uint16_t reg, uint8_t instance_id, uint32_t data); void data_fabric_write32(uint8_t function, uint16_t reg, uint8_t instance_id, uint32_t data);

15
src/soc/amd/picasso/include/soc/data_fabric.h
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@ -8,22 +8,11 @@
/* D18F0 - Fabric Configuration registers */ /* D18F0 - Fabric Configuration registers */
#define IOMS0_FABRIC_ID 9 #define IOMS0_FABRIC_ID 9
#define NUM_NB_MMIO_REGS 8
#define D18F0_VGAEN 0x80 #define D18F0_VGAEN 0x80
#define VGA_ADDR_ENABLE BIT(0) #define VGA_ADDR_ENABLE BIT(0)
#define D18F0_MMIO_BASE0 0x200
#define D18F0_MMIO_LIMIT0 0x204
#define D18F0_MMIO_SHIFT 16
#define D18F0_MMIO_CTRL0 0x208
#define MMIO_NP BIT(12)
#define MMIO_DST_FABRIC_ID_SHIFT 4
#define MMIO_WE BIT(1)
#define MMIO_RE BIT(0)
#define NUM_NB_MMIO_REGS 8
#define NB_MMIO_BASE(reg) ((reg) * 4 * sizeof(uint32_t) + D18F0_MMIO_BASE0)
#define NB_MMIO_LIMIT(reg) ((reg) * 4 * sizeof(uint32_t) + D18F0_MMIO_LIMIT0)
#define NB_MMIO_CONTROL(reg) ((reg) * 4 * sizeof(uint32_t) + D18F0_MMIO_CTRL0)
#define D18F0_DRAM_HOLE_CTL 0x104 #define D18F0_DRAM_HOLE_CTL 0x104
#define DRAM_HOLE_CTL_VALID BIT(0) #define DRAM_HOLE_CTL_VALID BIT(0)
#define DRAM_HOLE_CTL_BASE_SHFT 24 #define DRAM_HOLE_CTL_BASE_SHFT 24