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device: Replace ugly cases of dev_find_slot() 

These few cases lacked a proper devfn parameter in the
form of PCI_DEVFN(dev, fn).

Change-Id: Iad0b214df12dee65360d07e887a960b0c73a3e4f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/26481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This commit is contained in:
Kyösti Mälkki 2018-05-21 21:29:16 +03:00
parent ad7674ed00
commit 98a917443e
5 changed files with 10 additions and 10 deletions
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2
src/mainboard/emulation/qemu-i440fx/northbridge.c
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@ -53,7 +53,7 @@ static void cpu_pci_domain_set_resources(struct device *dev)
static void cpu_pci_domain_read_resources(struct device *dev)
{
u16 nbid = pci_read_config16(dev_find_slot(0, 0), PCI_DEVICE_ID);
u16 nbid = pci_read_config16(pcidev_on_root(0x0, 0), PCI_DEVICE_ID);
int i440fx = (nbid == 0x1237);
int q35 = (nbid == 0x29c0);
struct resource *res;

2
src/northbridge/intel/gm45/northbridge.c
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@ -289,7 +289,7 @@ static void gm45_init(void *const chip_info)
{
int dev, fn, bit_base;
struct device *const d0f0 = dev_find_slot(0, 0);
struct device *const d0f0 = pcidev_on_root(0x0, 0);
/* Hide internal functions based on devicetree info. */
for (dev = 3; dev > 0; --dev) {

2
src/northbridge/intel/x4x/northbridge.c
View File

@ -239,7 +239,7 @@ static void x4x_init(void *const chip_info)
{
int dev, fn, bit_base;
struct device *const d0f0 = dev_find_slot(0, 0);
struct device *const d0f0 = pcidev_on_root(0x0, 0);
/* Hide internal functions based on devicetree info. */
for (dev = 6; dev > 0; --dev) {

10
src/southbridge/amd/rs780/gfx.c
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@ -319,9 +319,9 @@ static void internal_gfx_pci_dev_init(struct device *dev)
u16 command;
u32 value;
u16 deviceid, vendorid;
struct device *nb_dev = dev_find_slot(0, 0);
struct device *k8_f2 = dev_find_slot(0, PCI_DEVFN(0x18, 2));
struct device *k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
struct device *nb_dev = pcidev_on_root(0x0, 0);
struct device *k8_f2 = pcidev_on_root(0x18, 2);
struct device *k8_f0 = pcidev_on_root(0x18, 0);
static const u8 ht_freq_lookup [] = {2, 0, 4, 0, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 0, 0, 28, 30, 32};
static const u8 ht_width_lookup [] = {8, 16, 0, 0, 2, 4, 0, 0};
static const u16 memclk_lookup_fam0F [] = {100, 0, 133, 0, 0, 166, 0, 200};
@ -733,7 +733,7 @@ static void internal_gfx_pci_dev_init(struct device *dev)
static void rs780_internal_gfx_disable(struct device *dev)
{
u32 l_dword;
struct device *nb_dev = dev_find_slot(0, 0);
struct device *nb_dev = pcidev_on_root(0x0, 0);
/* Disable internal GFX and enable external GFX. */
l_dword = pci_read_config32(nb_dev, 0x8c);
@ -753,7 +753,7 @@ static void rs780_internal_gfx_enable(struct device *dev)
{
u32 l_dword;
int i;
struct device *nb_dev = dev_find_slot(0, 0);
struct device *nb_dev = pcidev_on_root(0x0, 0);
msr_t sysmem;
#if !IS_ENABLED(CONFIG_GFXUMA)

4
src/southbridge/amd/sr5650/pcie.c
View File

@ -447,8 +447,8 @@ static void EnableLclkGating(struct device *dev)
u32 reg = 0;
u32 mask = 0;
u32 value = 0;
struct device *nb_dev = dev_find_slot(0, 0);
struct device *clk_f1= dev_find_slot(0, 1);
struct device *nb_dev = pcidev_on_root(0x0, 0);
struct device *clk_f1 = pcidev_on_root(0x0, 1);
reg = 0xE8;
port = dev->path.pci.devfn >> 3;