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src/device: Doxygen fixes 

- Add missing parameters
- add missing @param commands

Change-Id: I029b5dafde94bd250800b06c0e9bd2118f10ef48
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/8173
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
This commit is contained in:
Martin Roth 2015-01-06 21:02:52 -07:00
parent 97ccefdaf3
commit 98b698c94f
2 changed files with 12 additions and 3 deletions
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11
src/device/dram/ddr3.c
View File

@ -18,7 +18,7 @@
*/ */
/** /**
* @file ddr3_util.h * @file ddr3.c
* *
* \brief Utilities for decoding DDR3 SPDs * \brief Utilities for decoding DDR3 SPDs
*/ */
@ -452,8 +452,13 @@ static u16 ddr3_cas_to_mr0_map(u8 cas)
* write_recovery and cas are given in clock cycles. For example, a CAS of 7T * write_recovery and cas are given in clock cycles. For example, a CAS of 7T
* should be given as 7. * should be given as 7.
* *
* @param precharge_pd
* @param write_recovery Write recovery latency, tWR in clock cycles. * @param write_recovery Write recovery latency, tWR in clock cycles.
* @param dll_reset
* @param mode
* @param cas CAS latency in clock cycles. * @param cas CAS latency in clock cycles.
* @param burst_type
* @param burst_length
*/ */
mrs_cmd_t ddr3_get_mr0(enum ddr3_mr0_precharge precharge_pd, mrs_cmd_t ddr3_get_mr0(enum ddr3_mr0_precharge precharge_pd,
u8 write_recovery, u8 write_recovery,
@ -555,8 +560,12 @@ mrs_cmd_t ddr3_get_mr1(enum ddr3_mr1_qoff qoff,
* cas_cwl is given in clock cycles. For example, a cas_cwl of 7T should be * cas_cwl is given in clock cycles. For example, a cas_cwl of 7T should be
* given as 7. * given as 7.
* *
* @param rtt_wr
* @param extended_temp
* @param self_refresh
* @param cas_cwl CAS write latency in clock cycles. * @param cas_cwl CAS write latency in clock cycles.
*/ */
mrs_cmd_t ddr3_get_mr2(enum ddr3_mr2_rttwr rtt_wr, mrs_cmd_t ddr3_get_mr2(enum ddr3_mr2_rttwr rtt_wr,
enum ddr3_mr2_srt_range extended_temp, enum ddr3_mr2_srt_range extended_temp,
enum ddr3_mr2_asr self_refresh, u8 cas_cwl) enum ddr3_mr2_asr self_refresh, u8 cas_cwl)

4
src/device/pci_device.c
View File

@ -818,8 +818,8 @@ static struct device_operations *get_pci_bridge_ops(device_t dev)
* The driver entry can either point at a zero terminated array of acceptable * The driver entry can either point at a zero terminated array of acceptable
* device IDs, or include a single device ID. * device IDs, or include a single device ID.
* *
* @driver pointer to the PCI driver entry being checked * @param driver pointer to the PCI driver entry being checked
* @device_id PCI device ID of the device being matched * @param device_id PCI device ID of the device being matched
*/ */
static int device_id_match(struct pci_driver *driver, unsigned short device_id) static int device_id_match(struct pci_driver *driver, unsigned short device_id)
{ {