mb/siemens/mc_ehl1: Send POST codes to NC FPGA via PCI

This board does not have a LPC or eSPI connection to the NC FPGA anymore
and therefore IO port 0x80 is not useable for POST codes anymore. Enable
the feature of sending the POST codes to the NC FPGA via PCI so that the
POST codes are visbile again in coreboot.

Change-Id: I9043e4ec9a2ad6b946e373bb3dce9da3d42d00d1
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>

src/mainboard/siemens/mc_ehl/variants/mc_ehl1/Kconfig

@@ -4,6 +4,7 @@ config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select DRIVER_INTEL_I210
 	select INTEL_LPSS_UART_FOR_CONSOLE
+	select NC_FPGA_POST_CODE
 
 config FMDFILE
 	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/mc_ehl.fmd"
@@ -12,4 +13,19 @@ config UART_FOR_CONSOLE
 	int
 	default 2
 
+config EARLY_PCI_BRIDGE_DEVICE
+	hex
+	depends on NC_FPGA_POST_CODE
+	default 0x1c
+
+config EARLY_PCI_BRIDGE_FUNCTION
+	hex
+	depends on NC_FPGA_POST_CODE
+	default 0x2
+
+config EARLY_PCI_MMIO_BASE
+	hex
+	depends on NC_FPGA_POST_CODE
+	default 0xfe800000
+
 endif # BOARD_SIEMENS_MC_EHL1

src/mainboard/siemens/mc_ehl/variants/mc_ehl1/Makefile.inc

@@ -4,6 +4,8 @@ bootblock-y += gpio.c
 romstage-y += memory.c
 ramstage-y += gpio.c
 
+all-$(CONFIG_NC_FPGA_POST_CODE) += post.c
+
 SPD_SOURCES = mc_ehl1	# 0b000
 LIB_SPD_DEPS := $(foreach f, $(SPD_SOURCES), \
 			src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/spd/$(f).spd.hex)

src/mainboard/siemens/mc_ehl/variants/mc_ehl1/post.c

@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <nc_fpga.h>
+#include <types.h>
+
+void mainboard_post(uint8_t value)
+{
+	nc_fpga_post(value);
+}