diff --git a/src/cpu/intel/model_1067x/chip.h b/src/cpu/intel/model_1067x/chip.h deleted file mode 100644 index b298615e8a..0000000000 --- a/src/cpu/intel/model_1067x/chip.h +++ /dev/null @@ -1,7 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -struct cpu_intel_model_1067x_config { - int c5 : 1; - int c6 : 1; - int slfm : 1; -}; diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index 02e6032265..825a2468f9 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -9,25 +9,18 @@ #include #include -#include "chip.h" - #define MSR_BBL_CR_CTL3 0x11e static void configure_c_states(const int quad) { msr_t msr; - /* Find pointer to CPU configuration. */ - const struct device *lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); - const struct cpu_intel_model_1067x_config *const conf = - (lapic && lapic->chip_info) ? lapic->chip_info : NULL; - /* Is C5 requested and supported? */ - const int c5 = conf && conf->c5 && + const int c5 = southbridge_support_c5() && (rdmsr(MSR_BBL_CR_CTL3).lo & (3 << 30)) && !(rdmsr(MSR_FSB_FREQ).lo & (1 << 31)); /* Is C6 requested and supported? */ - const int c6 = conf && conf->c6 && + const int c6 = southbridge_support_c6() && ((cpuid_edx(5) >> (6 * 4)) & 0xf) && c5; const int cst_range = (c6 ? 6 : (c5 ? 5 : 4)) - 2; /* zero means lvl2 */ @@ -75,14 +68,9 @@ static void configure_p_states(const char stepping, const char cores) { msr_t msr; - /* Find pointer to CPU configuration. */ - const struct device *lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); - struct cpu_intel_model_1067x_config *const conf = - (lapic && lapic->chip_info) ? lapic->chip_info : NULL; - msr = rdmsr(MSR_EXTENDED_CONFIG); /* Super LFM supported? */ - if (conf && conf->slfm && (msr.lo & (1 << 27))) + if (northbridge_support_slfm() && (msr.lo & (1 << 27))) msr.lo |= (1 << 28); /* Enable Super LFM. */ wrmsr(MSR_EXTENDED_CONFIG, msr); diff --git a/src/include/cpu/intel/speedstep.h b/src/include/cpu/intel/speedstep.h index e085e34230..1a31c25bbf 100644 --- a/src/include/cpu/intel/speedstep.h +++ b/src/include/cpu/intel/speedstep.h @@ -3,11 +3,9 @@ #ifndef CPU_INTEL_SPEEDSTEP_H #define CPU_INTEL_SPEEDSTEP_H +#include #include -/* Magic value used to locate speedstep configuration in the device tree */ -#define SPEEDSTEP_APIC_MAGIC 0xACAC - /* MWAIT coordination I/O base address. This must match * the \_PR_.CP00 PM base address. */ @@ -92,4 +90,8 @@ void speedstep_gen_pstates(sst_table_t *); #define SPEEDSTEP_MIN_POWER_PENRYN 15000 #define SPEEDSTEP_SLFM_POWER_PENRYN 12000 +bool southbridge_support_c5(void); +bool southbridge_support_c6(void); +bool northbridge_support_slfm(void); + #endif /* CPU_INTEL_SPEEDSTEP_H */ diff --git a/src/mainboard/acer/g43t-am3/devicetree.cb b/src/mainboard/acer/g43t-am3/devicetree.cb index 713ac40d2f..1f2bc08fac 100644 --- a/src/mainboard/acer/g43t-am3/devicetree.cb +++ b/src/mainboard/acer/g43t-am3/devicetree.cb @@ -6,9 +6,6 @@ chip northbridge/intel/x4x # Northbridge chip cpu/intel/socket_LGA775 device lapic 0 on end end - chip cpu/intel/model_1067x # CPU - device lapic 0xacac off end - end end device domain 0 on ops x4x_pci_domain_ops # PCI domain diff --git a/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb index 846a02b676..28b24d8742 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb @@ -6,9 +6,6 @@ chip northbridge/intel/x4x # Northbridge chip cpu/intel/socket_LGA775 device lapic 0 on end end - chip cpu/intel/model_1067x # CPU - device lapic 0xACAC off end - end end device domain 0 on ops x4x_pci_domain_ops # PCI domain diff --git a/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb index 8115430cd6..7daa4a479e 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb @@ -6,9 +6,6 @@ chip northbridge/intel/x4x # Northbridge chip cpu/intel/socket_LGA775 device lapic 0 on end end - chip cpu/intel/model_1067x # CPU - device lapic 0xACAC off end - end end device domain 0 on ops x4x_pci_domain_ops # PCI domain diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb index ef019d1ac2..a5d205cb63 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb @@ -6,9 +6,6 @@ chip northbridge/intel/x4x # Northbridge chip cpu/intel/socket_LGA775 device lapic 0 on end end - chip cpu/intel/model_1067x # CPU - device lapic 0xACAC off end - end end device domain 0 on ops x4x_pci_domain_ops # PCI domain diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb index 4237041af7..83fc04094a 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb @@ -6,9 +6,6 @@ chip northbridge/intel/x4x # Northbridge chip cpu/intel/socket_LGA775 device lapic 0 on end end - chip cpu/intel/model_1067x # CPU - device lapic 0xACAC off end - end end device domain 0 on ops x4x_pci_domain_ops # PCI domain diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb index 23268f2bdf..0dbe8d9685 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb @@ -6,9 +6,6 @@ chip northbridge/intel/x4x # Northbridge chip cpu/intel/socket_LGA775 device lapic 0 on end end - chip cpu/intel/model_1067x # CPU - device lapic 0xACAC off end - end end device domain 0 on ops x4x_pci_domain_ops # PCI domain diff --git a/src/mainboard/asus/p5gc-mx/devicetree.cb b/src/mainboard/asus/p5gc-mx/devicetree.cb index a9cad93e33..823882650e 100644 --- a/src/mainboard/asus/p5gc-mx/devicetree.cb +++ b/src/mainboard/asus/p5gc-mx/devicetree.cb @@ -7,9 +7,6 @@ chip northbridge/intel/i945 chip cpu/intel/socket_LGA775 device lapic 0 on end end - chip cpu/intel/model_1067x - device lapic 0xACAC off end - end end device domain 0 on diff --git a/src/mainboard/asus/p5qc/variants/p5q/devicetree.cb b/src/mainboard/asus/p5qc/variants/p5q/devicetree.cb index c452672d92..d7d465508c 100644 --- a/src/mainboard/asus/p5qc/variants/p5q/devicetree.cb +++ b/src/mainboard/asus/p5qc/variants/p5q/devicetree.cb @@ -6,9 +6,6 @@ chip northbridge/intel/x4x # Northbridge chip cpu/intel/socket_LGA775 device lapic 0 on end end - chip cpu/intel/model_1067x # CPU - device lapic 0xACAC off end - end end device domain 0 on ops x4x_pci_domain_ops # PCI domain diff --git a/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb b/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb index b0452d4d57..d6dbc2dd44 100644 --- a/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb +++ b/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb @@ -6,9 +6,6 @@ chip northbridge/intel/x4x # Northbridge chip cpu/intel/socket_LGA775 device lapic 0 on end end - chip cpu/intel/model_1067x # CPU - device lapic 0xacac off end - end end device domain 0 on ops x4x_pci_domain_ops # PCI domain diff --git a/src/mainboard/asus/p5qc/variants/p5q_se/devicetree.cb b/src/mainboard/asus/p5qc/variants/p5q_se/devicetree.cb index 8390bc0f92..f099ab297d 100644 --- a/src/mainboard/asus/p5qc/variants/p5q_se/devicetree.cb +++ b/src/mainboard/asus/p5qc/variants/p5q_se/devicetree.cb @@ -6,9 +6,6 @@ chip northbridge/intel/x4x # Northbridge chip cpu/intel/socket_LGA775 device lapic 0 on end end - chip cpu/intel/model_1067x # CPU - device lapic 0xacac off end - end end device domain 0 on ops x4x_pci_domain_ops # PCI domain diff --git a/src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb b/src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb index 70e82e84e8..54f9dcfd3e 100644 --- a/src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb +++ b/src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb @@ -6,9 +6,6 @@ chip northbridge/intel/x4x # Northbridge chip cpu/intel/socket_LGA775 device lapic 0 on end end - chip cpu/intel/model_1067x # CPU - device lapic 0xacac off end - end end device domain 0 on ops x4x_pci_domain_ops # PCI domain diff --git a/src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb b/src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb index 8390bc0f92..f099ab297d 100644 --- a/src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb +++ b/src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb @@ -6,9 +6,6 @@ chip northbridge/intel/x4x # Northbridge chip cpu/intel/socket_LGA775 device lapic 0 on end end - chip cpu/intel/model_1067x # CPU - device lapic 0xacac off end - end end device domain 0 on ops x4x_pci_domain_ops # PCI domain diff --git a/src/mainboard/asus/p5ql-em/devicetree.cb b/src/mainboard/asus/p5ql-em/devicetree.cb index a839b9dda1..8e061f24a5 100644 --- a/src/mainboard/asus/p5ql-em/devicetree.cb +++ b/src/mainboard/asus/p5ql-em/devicetree.cb @@ -6,9 +6,6 @@ chip northbridge/intel/x4x # Northbridge chip cpu/intel/socket_LGA775 device lapic 0 on end end - chip cpu/intel/model_1067x # CPU - device lapic 0xacac off end - end end device domain 0 on ops x4x_pci_domain_ops # PCI domain diff --git a/src/mainboard/asus/p5qpl-am/devicetree.cb b/src/mainboard/asus/p5qpl-am/devicetree.cb index 104485116e..602ba576f4 100644 --- a/src/mainboard/asus/p5qpl-am/devicetree.cb +++ b/src/mainboard/asus/p5qpl-am/devicetree.cb @@ -6,9 +6,6 @@ chip northbridge/intel/x4x # Northbridge chip cpu/intel/socket_LGA775 device lapic 0 on end end - chip cpu/intel/model_1067x # CPU - device lapic 0xacac off end - end end device domain 0 on ops x4x_pci_domain_ops # PCI domain diff --git a/src/mainboard/foxconn/g41s-k/devicetree.cb b/src/mainboard/foxconn/g41s-k/devicetree.cb index 46bb4228cb..af15577158 100644 --- a/src/mainboard/foxconn/g41s-k/devicetree.cb +++ b/src/mainboard/foxconn/g41s-k/devicetree.cb @@ -6,9 +6,6 @@ chip northbridge/intel/x4x # Northbridge chip cpu/intel/socket_LGA775 device lapic 0 on end end - chip cpu/intel/model_1067x # CPU - device lapic 0xACAC off end - end end device domain 0 on ops x4x_pci_domain_ops # PCI domain diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb index 673172dd5e..5064cd9428 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb @@ -7,9 +7,6 @@ chip northbridge/intel/i945 chip cpu/intel/socket_LGA775 device lapic 0 on end end - chip cpu/intel/model_1067x - device lapic 0xACAC off end - end end register "pci_mmio_size" = "768" diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb index 3a4ae45cda..5ec31eb18a 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb @@ -6,9 +6,6 @@ chip northbridge/intel/x4x # Northbridge chip cpu/intel/socket_LGA775 device lapic 0 on end end - chip cpu/intel/model_1067x # CPU - device lapic 0xACAC off end - end end device domain 0 on ops x4x_pci_domain_ops # PCI domain diff --git a/src/mainboard/intel/dg41wv/devicetree.cb b/src/mainboard/intel/dg41wv/devicetree.cb index 641ada5fc8..06617f6aae 100644 --- a/src/mainboard/intel/dg41wv/devicetree.cb +++ b/src/mainboard/intel/dg41wv/devicetree.cb @@ -6,9 +6,6 @@ chip northbridge/intel/x4x # Northbridge chip cpu/intel/socket_LGA775 device lapic 0 on end end - chip cpu/intel/model_1067x # CPU - device lapic 0xACAC off end - end end device domain 0 on ops x4x_pci_domain_ops # PCI domain diff --git a/src/mainboard/intel/dg43gt/devicetree.cb b/src/mainboard/intel/dg43gt/devicetree.cb index 5e2eb9d60b..80d2bf7d63 100644 --- a/src/mainboard/intel/dg43gt/devicetree.cb +++ b/src/mainboard/intel/dg43gt/devicetree.cb @@ -6,9 +6,6 @@ chip northbridge/intel/x4x # Northbridge chip cpu/intel/socket_LGA775 device lapic 0 on end end - chip cpu/intel/model_1067x # CPU - device lapic 0xacac off end - end end device domain 0 on ops x4x_pci_domain_ops # PCI domain diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb index 0bfdbc95aa..7946e34bb2 100644 --- a/src/mainboard/lenovo/t400/devicetree.cb +++ b/src/mainboard/lenovo/t400/devicetree.cb @@ -8,22 +8,13 @@ chip northbridge/intel/gm45 register "gpu_panel_power_backlight_off_delay" = "2500" # Tx: 250ms register "gpu_panel_power_cycle_delay" = "3" # T4: 200ms + register "slfm" = "1" + device cpu_cluster 0 on ops gm45_cpu_bus_ops chip cpu/intel/socket_p device lapic 0 on end end - chip cpu/intel/model_1067x - # Magic APIC ID to locate this chip - device lapic 0xACAC off end - - # Enable Super LFM - register "slfm" = "1" - - # Enable C5, C6 - register "c5" = "1" - register "c6" = "1" - end end register "pci_mmio_size" = "2048" diff --git a/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb b/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb index 9a2c452fb9..a8dea8db4b 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb +++ b/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb @@ -6,9 +6,6 @@ chip northbridge/intel/x4x # Northbridge chip cpu/intel/socket_LGA775 device lapic 0 on end end - chip cpu/intel/model_1067x # CPU - device lapic 0xACAC off end - end end device domain 0 on ops x4x_pci_domain_ops # PCI domain diff --git a/src/mainboard/lenovo/x200/devicetree.cb b/src/mainboard/lenovo/x200/devicetree.cb index dc059f0d50..814491bacc 100644 --- a/src/mainboard/lenovo/x200/devicetree.cb +++ b/src/mainboard/lenovo/x200/devicetree.cb @@ -8,22 +8,13 @@ chip northbridge/intel/gm45 register "gpu_panel_power_backlight_off_delay" = "2500" # Tx: 250ms register "gpu_panel_power_cycle_delay" = "3" # T4: 200ms + register "slfm" = "1" + device cpu_cluster 0 on ops gm45_cpu_bus_ops chip cpu/intel/socket_BGA956 device lapic 0 on end end - chip cpu/intel/model_1067x - # Magic APIC ID to locate this chip - device lapic 0xACAC off end - - # Enable Super LFM - register "slfm" = "1" - - # Enable C5, C6 - register "c5" = "1" - register "c6" = "1" - end end register "pci_mmio_size" = "2048" diff --git a/src/mainboard/roda/rk9/devicetree.cb b/src/mainboard/roda/rk9/devicetree.cb index d4b4aef69a..bb2cd70494 100644 --- a/src/mainboard/roda/rk9/devicetree.cb +++ b/src/mainboard/roda/rk9/devicetree.cb @@ -1,22 +1,12 @@ chip northbridge/intel/gm45 # IGD Displays register "gfx" = "GMA_STATIC_DISPLAYS(0)" + register "slfm" = "1" device cpu_cluster 0 on ops gm45_cpu_bus_ops chip cpu/intel/socket_BGA956 device lapic 0 on end end - chip cpu/intel/model_1067x - # Magic APIC ID to locate this chip - device lapic 0xACAC off end - - # Enable Super LFM - register "slfm" = "1" - - # Enable C5, C6 - register "c5" = "1" - register "c6" = "1" - end end register "pci_mmio_size" = "2048" diff --git a/src/northbridge/intel/gm45/chip.h b/src/northbridge/intel/gm45/chip.h index 0d09bb40ef..76ceccac6e 100644 --- a/src/northbridge/intel/gm45/chip.h +++ b/src/northbridge/intel/gm45/chip.h @@ -19,6 +19,7 @@ struct northbridge_intel_gm45_config { * Maximum PCI mmio size in MiB. */ u16 pci_mmio_size; + int slfm; }; #endif /* NORTHBRIDGE_INTEL_GM45_CHIP_H */ diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index 31e3de46dc..c6fa0e065c 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -257,3 +258,10 @@ struct chip_operations northbridge_intel_gm45_ops = { CHIP_NAME("Intel GM45 Northbridge") .init = gm45_init, }; + +bool northbridge_support_slfm(void) +{ + struct device *gmch = __pci_0_00_0; + struct northbridge_intel_gm45_config *config = gmch->chip_info; + return config->slfm == 1; +} diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index c175576d3a..00276562d8 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -10,6 +10,7 @@ #include #include #include +#include #include "i945.h" static void mch_domain_read_resources(struct device *dev) @@ -164,3 +165,8 @@ struct device_operations i945_cpu_bus_ops = { struct chip_operations northbridge_intel_i945_ops = { CHIP_NAME("Intel i945 Northbridge") }; + +bool northbridge_support_slfm(void) +{ + return false; +} diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index da046d1697..cfa57ada49 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -12,6 +12,7 @@ #include #include #include +#include static void mch_domain_read_resources(struct device *dev) { @@ -194,3 +195,8 @@ struct chip_operations northbridge_intel_x4x_ops = { CHIP_NAME("Intel 4-Series Northbridge") .init = x4x_init, }; + +bool northbridge_support_slfm(void) +{ + return false; +} diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index fd0a203efa..69c1469b63 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -473,3 +474,13 @@ static const struct pci_driver ich7_lpc __pci_driver = { .vendor = PCI_VID_INTEL, .devices = pci_device_ids, }; + +bool southbridge_support_c5(void) +{ + return false; +} + +bool southbridge_support_c6(void) +{ + return false; +} diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 24b8a27e63..d897130e42 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -137,6 +138,20 @@ static void i82801ix_gpi_routing(struct device *dev) pci_write_config32(dev, D31F0_GPIO_ROUT, reg32); } +bool southbridge_support_c5(void) +{ + struct device *lpc_dev = __pci_0_1f_0; + struct southbridge_intel_i82801ix_config *config = lpc_dev->chip_info; + return config->c5_enable == 1; +} + +bool southbridge_support_c6(void) +{ + struct device *lpc_dev = __pci_0_1f_0; + struct southbridge_intel_i82801ix_config *config = lpc_dev->chip_info; + return config->c6_enable == 1; +} + static void i82801ix_power_options(struct device *dev) { u8 reg8; @@ -216,15 +231,15 @@ static void i82801ix_power_options(struct device *dev) reg16 |= (1 << 10); // BIOS_PCI_EXP_EN - Desktop/Mobile only if (CONFIG(DEBUG_PERIODIC_SMI)) reg16 |= (3 << 0); // Periodic SMI every 8s - if (config->c5_enable) + if (southbridge_support_c5()) reg16 |= (1 << 11); /* Enable C5, C6 and PMSYNC# */ pci_write_config16(dev, D31F0_GEN_PMCON_1, reg16); /* Set exit timings for C5/C6. */ - if (config->c5_enable) { + if (southbridge_support_c5()) { reg8 = pci_read_config8(dev, D31F0_C5_EXIT_TIMING); reg8 &= ~((7 << 3) | (7 << 0)); - if (config->c6_enable) + if (southbridge_support_c6()) reg8 |= (5 << 3) | (3 << 0); /* 38-44us PMSYNC# to STPCLK#, 95-102us DPRSTP# to STP_CPU# */ else diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index 39b662a1a7..ead2b8ad9b 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include "chip.h" @@ -139,6 +140,20 @@ static void i82801jx_gpi_routing(struct device *dev) pci_write_config32(dev, D31F0_GPIO_ROUT, reg32); } +bool southbridge_support_c5(void) +{ + struct device *lpc_dev = __pci_0_1f_0; + struct southbridge_intel_i82801jx_config *config = lpc_dev->chip_info; + return config->c5_enable == 1; +} + +bool southbridge_support_c6(void) +{ + struct device *lpc_dev = __pci_0_1f_0; + struct southbridge_intel_i82801jx_config *config = lpc_dev->chip_info; + return config->c6_enable == 1; +} + static void i82801jx_power_options(struct device *dev) { u8 reg8; @@ -218,15 +233,15 @@ static void i82801jx_power_options(struct device *dev) reg16 |= (1 << 10); // BIOS_PCI_EXP_EN - Desktop/Mobile only if (CONFIG(DEBUG_PERIODIC_SMI)) reg16 |= (3 << 0); // Periodic SMI every 8s - if (config->c5_enable) + if (southbridge_support_c5()) reg16 |= (1 << 11); /* Enable C5, C6 and PMSYNC# */ pci_write_config16(dev, D31F0_GEN_PMCON_1, reg16); /* Set exit timings for C5/C6. */ - if (config->c5_enable) { + if (southbridge_support_c5()) { reg8 = pci_read_config8(dev, D31F0_C5_EXIT_TIMING); reg8 &= ~((7 << 3) | (7 << 0)); - if (config->c6_enable) + if (southbridge_support_c6()) reg8 |= (5 << 3) | (3 << 0); /* 38-44us PMSYNC# to STPCLK#, 95-102us DPRSTP# to STP_CPU# */ else