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soc/intel/common: Abstract the sideband access 

The existing Sideband access is with the PCH P2SB. There will be future
platforms which access the TCSS registers through SBI other than the PCH
P2SB. This change abstracts the SBI with common API.

BUG=b:213574324
TEST=Build platforms coreboot images successfully.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Ia6201762fe92801ce6b4ed97d0eac23ac71ccd37
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60978
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
John Zhao 2022-01-10 10:51:24 -08:00 committed by Subrata Banik
parent 0f76a18c3a
commit 98ce39dce4
4 changed files with 9 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/soc/intel/common/block/cse/disable_heci.c
View File

@ -36,7 +36,7 @@ void heci_disable(void)
p2sb_unhide();
/* Send SBI command to make HECI#1 function disable */
status = pcr_execute_sideband_msg(&msg, &data32, &response);
status = pcr_execute_sideband_msg(PCH_DEV_P2SB, &msg, &data32, &response);
if (status || response)
printk(BIOS_ERR, "Fail to make CSME function disable\n");

7
src/soc/intel/common/block/gpio/gpio.c
View File

@ -1,5 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#define __SIMPLE_DEVICE__
#include <assert.h>
#include <bootstate.h>
#include <console/console.h>
@ -10,6 +12,7 @@
#include <intelblocks/itss.h>
#include <intelblocks/p2sb.h>
#include <intelblocks/pcr.h>
#include <soc/pci_devs.h>
#include <soc/pm.h>
#include <stdlib.h>
#include <types.h>
@ -531,7 +534,7 @@ int gpio_lock_pads(const struct gpio_lock_config *pad_list, const size_t count)
if (CONFIG(DEBUG_GPIO))
printk(BIOS_INFO, "%s: Locking pad %d configuration\n",
__func__, pad);
status = pcr_execute_sideband_msg(&msg, &data, &response);
status = pcr_execute_sideband_msg(PCH_DEV_P2SB, &msg, &data, &response);
if ((err = sideband_msg_err(status, response)) != 0) {
err_response = err;
continue;
@ -543,7 +546,7 @@ int gpio_lock_pads(const struct gpio_lock_config *pad_list, const size_t count)
printk(BIOS_INFO, "%s: Locking pad %d TX state\n",
__func__, pad);
msg.offset += sizeof(uint32_t);
status = pcr_execute_sideband_msg(&msg, &data, &response);
status = pcr_execute_sideband_msg(PCH_DEV_P2SB, &msg, &data, &response);
if ((err = sideband_msg_err(status, response)) != 0) {
err_response = err;
continue;

3
src/soc/intel/common/block/include/intelblocks/pcr.h
View File

@ -8,6 +8,7 @@
#if !defined(__ACPI__)
#include <types.h>
#include <device/pci_ops.h>
uint32_t pcr_read32(uint8_t pid, uint16_t offset);
uint16_t pcr_read16(uint8_t pid, uint16_t offset);
@ -62,7 +63,7 @@ struct pcr_sbi_msg {
* 0: SBI message is successfully completed
* -1: SBI message failure
*/
int pcr_execute_sideband_msg(struct pcr_sbi_msg *msg, uint32_t *data,
int pcr_execute_sideband_msg(pci_devfn_t dev, struct pcr_sbi_msg *msg, uint32_t *data,
uint8_t *response);
/* Get the starting address of the port's registers. */

3
src/soc/intel/common/block/pcr/pcr.c
View File

@ -240,10 +240,9 @@ static int pcr_wait_for_completion(const pci_devfn_t dev)
* 0: SBI message is successfully completed
* -1: SBI message failure
*/
int pcr_execute_sideband_msg(struct pcr_sbi_msg *msg, uint32_t *data,
int pcr_execute_sideband_msg(pci_devfn_t dev, struct pcr_sbi_msg *msg, uint32_t *data,
uint8_t *response)
{
const pci_devfn_t dev = PCH_DEV_P2SB;
uint32_t sbi_data;
uint16_t sbi_status;
uint16_t sbi_rid;