soc/intel/cannonlake: Allow RP#1 usage for ClkSrc
0 is converted to not used, so use a special value to allow using PCIe root port #1. Change-Id: I2d64afc9bb4627913492edad8f36566e7fb18166 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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@ -349,6 +349,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
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for (i = 0; i < ARRAY_SIZE(config->PcieClkSrcUsage); i++) {
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if (config->PcieClkSrcUsage[i] == 0)
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config->PcieClkSrcUsage[i] = PCIE_CLK_NOTUSED;
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else if (config->PcieClkSrcUsage[i] == PCIE_CLK_RP0)
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config->PcieClkSrcUsage[i] = 0;
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}
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memcpy(params->PcieClkSrcUsage, config->PcieClkSrcUsage,
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sizeof(config->PcieClkSrcUsage));
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@ -10,5 +10,7 @@
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#define PCIE_CLK_NOTUSED 0xFF
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#define PCIE_CLK_LAN 0x70
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#define PCIE_CLK_FREE 0x80
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/* Converted to 0, allows 0 to be notused */
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#define PCIE_CLK_RP0 0xFE
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#endif
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