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soc/intel/cannonlake: Allow RP#1 usage for ClkSrc

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0 is converted to not used, so use a special value to allow using PCIe
root port #1.

Change-Id: I2d64afc9bb4627913492edad8f36566e7fb18166
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This commit is contained in:
Jeremy Soller 2020-12-29 11:17:28 -07:00 committed by Patrick Georgi
parent 3b6b9c7b78
commit 98d580b8fb
2 changed files with 4 additions and 0 deletions
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2
src/soc/intel/cannonlake/fsp_params.c
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@ -349,6 +349,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
for (i = 0; i < ARRAY_SIZE(config->PcieClkSrcUsage); i++) {
if (config->PcieClkSrcUsage[i] == 0)
config->PcieClkSrcUsage[i] = PCIE_CLK_NOTUSED;
else if (config->PcieClkSrcUsage[i] == PCIE_CLK_RP0)
config->PcieClkSrcUsage[i] = 0;
}
memcpy(params->PcieClkSrcUsage, config->PcieClkSrcUsage,
sizeof(config->PcieClkSrcUsage));

2
src/soc/intel/cannonlake/include/soc/pch.h
View file

@ -10,5 +10,7 @@
#define PCIE_CLK_NOTUSED 0xFF
#define PCIE_CLK_LAN 0x70
#define PCIE_CLK_FREE 0x80
/* Converted to 0, allows 0 to be notused */
#define PCIE_CLK_RP0 0xFE
#endif