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src/superio/nuvoton: Add support for NCT5539D 

Values taken from NCT5539D datasheet V1.1 (June 30th, 2015).

Change-Id: I7e979bde53ce3dac1a4f74e7e51a3c6a0149051c
Signed-off-by: Pavel Sayekat <pavelsayekat@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33842
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Pavel Sayekat 2019-07-01 19:53:29 +06:00 committed by Felix Held
parent 931e991325
commit 98d5a86ec0
6 changed files with 187 additions and 0 deletions
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1
src/superio/nuvoton/Makefile.inc
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@ -19,6 +19,7 @@ romstage-$(CONFIG_SUPERIO_NUVOTON_COMMON_PRE_RAM) += common/early_serial.c
subdirs-$(CONFIG_SUPERIO_NUVOTON_WPCM450) += wpcm450
subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT5104D) += nct5104d
subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT5539D) += nct5539d
subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT5572D) += nct5572d
subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT6776) += nct6776
subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT6779D) += nct6779d

4
src/superio/nuvoton/common/early_serial.c
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@ -65,6 +65,10 @@ void nuvoton_enable_serial(pnp_devfn_t dev, u16 iobase)
{
nuvoton_pnp_enter_conf_state(dev);
if (CONFIG(SUPERIO_NUVOTON_NCT5539D_COM_A))
/* Route COM A to GPIO8 pin group */
pnp_write_config(dev, 0x2a, 0x40);
if (CONFIG(SUPERIO_NUVOTON_NCT6776_COM_A))
/* Route COM A to GPIO8 pin group */
pnp_write_config(dev, 0x2a, 0x40);

23
src/superio/nuvoton/nct5539d/Kconfig Normal file
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@ -0,0 +1,23 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2019 Pavel Sayekat <pavelsayekat@gmail.com>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
config SUPERIO_NUVOTON_NCT5539D
bool
select SUPERIO_NUVOTON_COMMON_PRE_RAM
config SUPERIO_NUVOTON_NCT5539D_COM_A
bool
depends on SUPERIO_NUVOTON_NCT5539D
default n

16
src/superio/nuvoton/nct5539d/Makefile.inc Normal file
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@ -0,0 +1,16 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2019 Pavel Sayekat <pavelsayekat@gmail.com>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT5539D) += superio.c

51
src/superio/nuvoton/nct5539d/nct5539d.h Normal file
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@ -0,0 +1,51 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2019 Pavel Sayekat <pavelsayekat@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef SUPERIO_NUVOTON_NCT5539D_H
#define SUPERIO_NUVOTON_NCT5539D_H
/* Logical Device Numbers (LDN). */
#define NCT5539D_SP1 0x02 /* UART A */
#define NCT5539D_KBC 0x05 /* Keyboard Controller */
#define NCT5539D_CIR 0x06 /* Consumer IR */
#define NCT5539D_GPIO78 0x07 /* GPIO 7 & 8 */
#define NCT5539D_WDT1_WDT3_GPIO0 0x08 /* WDT1, WDT3, GPIO 0 & KBC P20 */
#define NCT5539D_GPIO2345 0x09 /* GPIO 2, 3, 4 & 5 */
#define NCT5539D_ACPI 0x0A /* ACPI */
#define NCT5539D_HWM_FPLED 0x0B /* HW Monitor, Front Panel LED */
#define NCT5539D_WDT2 0x0D /* WDT2 */
#define NCT5539D_CIRWUP 0x0E /* CIR Wake-Up */
#define NCT5539D_GPIO_PP_OD 0x0F /* GPIO Push-Pull/Open-Drain */
#define NCT5539D_GPIO_PSO 0x11 /* GPIO, RI PSOUT Wake-Up Status */
#define NCT5539D_SWEC 0x12 /* SW Error Control */
#define NCT5539D_FLED 0x15 /* Fading LED */
#define NCT5539D_DS 0x16 /* Deep Sleep */
/* Virtual LDNs */
#define NCT5539D_WDT1 ((0 << 8) | NCT5539D_WDT1_WDT3_GPIO0)
#define NCT5539D_WDT3 ((4 << 8) | NCT5539D_WDT1_WDT3_GPIO0)
#define NCT5539D_GPIOBASE ((3 << 8) | NCT5539D_WDT1_WDT3_GPIO0)
#define NCT5539D_GPIO0 ((1 << 8) | NCT5539D_WDT1_WDT3_GPIO0)
#define NCT5539D_GPIO2 ((0 << 8) | NCT5539D_GPIO2345)
#define NCT5539D_GPIO3 ((1 << 8) | NCT5539D_GPIO2345)
#define NCT5539D_GPIO4 ((2 << 8) | NCT5539D_GPIO2345)
#define NCT5539D_GPIO5 ((3 << 8) | NCT5539D_GPIO2345)
#define NCT5539D_GPIO7 ((1 << 8) | NCT5539D_GPIO78)
#define NCT5539D_GPIO8 ((2 << 8) | NCT5539D_GPIO78)
#define NCT5539D_DS5 ((0 << 8) | NCT5539D_DS)
#define NCT5539D_DS3 ((1 << 8) | NCT5539D_DS)
#endif /* SUPERIO_NUVOTON_NCT5539D_H */

92
src/superio/nuvoton/nct5539d/superio.c Normal file
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@ -0,0 +1,92 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Advanced Micro Devices, Inc.
* Copyright (C) 2014 Felix Held <felix-coreboot@felixheld.de>
* Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>
* Copyright (C) 2015 Matt DeVillier <matt.devillier@gmail.com>
* Copyright (C) 2016 Omar Pakker <omarpakker+coreboot@gmail.com>
* Copyright (C) 2019 Pavel Sayekat <pavelsayekat@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <device/device.h>
#include <device/pnp.h>
#include <pc80/keyboard.h>
#include <stdlib.h>
#include <superio/conf_mode.h>
#include "nct5539d.h"
static void nct5539d_init(struct device *dev)
{
if (!dev->enabled)
return;
switch (dev->path.pnp.device) {
case NCT5539D_KBC:
pc_keyboard_init(NO_AUX_DEVICE);
break;
}
}
static struct device_operations ops = {
.read_resources = pnp_read_resources,
.set_resources = pnp_set_resources,
.enable_resources = pnp_enable_resources,
.enable = pnp_alt_enable,
.init = nct5539d_init,
.ops_pnp_mode = &pnp_conf_mode_8787_aa,
};
static struct pnp_info pnp_dev_info[] = {
{ NULL, NCT5539D_SP1, PNP_IO0 | PNP_IRQ0,
0x0ff8, },
{ NULL, NCT5539D_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1,
0x0fff, 0x0fff, },
{ NULL, NCT5539D_CIR, PNP_IO0 | PNP_IRQ0,
0x0ff8, },
{ NULL, NCT5539D_ACPI},
{ NULL, NCT5539D_HWM_FPLED, PNP_IO0 | PNP_IRQ0,
0x0ffe, 0x0ffe, },
{ NULL, NCT5539D_WDT2},
{ NULL, NCT5539D_CIRWUP, PNP_IO0 | PNP_IRQ0,
0x0ff8, },
{ NULL, NCT5539D_GPIO_PP_OD},
{ NULL, NCT5539D_WDT1},
{ NULL, NCT5539D_WDT3},
{ NULL, NCT5539D_GPIOBASE, PNP_IO0,
0x0ff8, },
{ NULL, NCT5539D_GPIO0},
{ NULL, NCT5539D_GPIO2},
{ NULL, NCT5539D_GPIO3},
{ NULL, NCT5539D_GPIO4},
{ NULL, NCT5539D_GPIO5},
{ NULL, NCT5539D_GPIO7},
{ NULL, NCT5539D_GPIO8},
{ NULL, NCT5539D_GPIO_PSO},
{ NULL, NCT5539D_SWEC},
{ NULL, NCT5539D_FLED},
{ NULL, NCT5539D_DS5},
{ NULL, NCT5539D_DS3},
};
static void enable_dev(struct device *dev)
{
pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
}
struct chip_operations superio_nuvoton_nct5539d_ops = {
CHIP_NAME("NUVOTON NCT5539D Super I/O")
.enable_dev = enable_dev,
};