AMD Bald Eagle: Add binary PI vendorcode files

Add all of the PI source that will remain part of coreboot to
build with a binary AGESA PI BLOB.  This includes the gcc makefiles,
some Kconfig, and the AGESA standard library functions.

Change vendorcode Makefile and Kconfig so that they can compile
AMD library files and use headers from outside the coreboot/src
tree.

This fix changes the makefile so that the AGESA dispatcher is
built using its own rules rather than generic library generation
rules in coreboot/Makefile and coreboot/Makefile.inc.  The AGESA
source files are initially copied from whereever they live into
coreboot/build/agesa.  They are compiled from there.  The binary
PI directory now has a mandatory structure that places the AGESA
BLOB into the same directory as the support headers.  These will
nominally be placed in the amd directory in SageBIOS or the
3rdparty directory in coreboot.org.

Change-Id: I56788cd197159939b64c7d16c1d32418f8cc2197
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/5967
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>

src/vendorcode/amd/pi/00630F01/Kconfig

@@ -0,0 +1,55 @@
+#
+# Copyright (c) 2013 - 2014, Sage Electronic Engineering, LLC
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#     * Redistributions of source code must retain the above copyright
+#       notice, this list of conditions and the following disclaimer.
+#     * Redistributions in binary form must reproduce the above copyright
+#       notice, this list of conditions and the following disclaimer in the
+#       documentation and/or other materials provided with the distribution.
+#     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+#       its contributors may be used to endorse or promote products derived
+#       from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+if CPU_AMD_PI_00630F01
+
+config AGESA_BINARY_PI_DEFAULTS # dummy
+	def_bool y
+	select AGESA_BINARY_PI_LOCATION_DEFAULT_SELECTED
+	select AGESA_BINARY_PI_PATH_DEFAULT_SELECTED
+	select AGESA_BINARY_PI_FILE_DEFAULT_SELECTED
+
+config AGESA_BINARY_PI_PATH_DEFAULT
+	string
+	default "3rdparty/pi/amd/00630F01"
+	help
+	  The default binary file name to use for AMD platform initialization.
+
+config AGESA_BINARY_PI_FILE_DEFAULT
+	string
+	default "FP3/AGESA.bin"
+	help
+	  The default binary file name to use for AMD platform initialization.
+
+config AGESA_BINARY_PI_LOCATION_DEFAULT
+	hex
+	default 0xFFE00000
+	help
+	  The default ROM address at which to store the binary Platform
+	  Initialization code.
+
+endif

src/vendorcode/amd/pi/00630F01/Lib/amdlib.h

@@ -0,0 +1,393 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Library
+ *
+ * Contains interface to the AMD AGESA library
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Lib
+ * @e \$Revision: 85030 $   @e \$Date: 2012-12-26 00:20:10 -0600 (Wed, 26 Dec 2012) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ *               2013 - 2014, Sage Electronic Engineering, LLC
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************
+ **/
+
+#ifndef _AMD_LIB_H_
+#define _AMD_LIB_H_
+
+#define IOCF8 0xCF8
+#define IOCFC 0xCFC
+
+// Reg Values for ReadCpuReg and WriteCpuReg
+#define    CR4_REG  0x04
+#define    DR0_REG  0x10
+#define    DR1_REG  0x11
+#define    DR2_REG  0x12
+#define    DR3_REG  0x13
+#define    DR7_REG  0x17
+
+// PROTOTYPES FOR amdlib32.asm
+UINT8
+ReadIo8 (
+  IN       UINT16 Address
+  );
+
+UINT16
+ReadIo16 (
+  IN       UINT16 Address
+  );
+
+UINT32
+ReadIo32 (
+  IN       UINT16 Address
+  );
+
+VOID
+WriteIo8 (
+  IN       UINT16 Address,
+  IN       UINT8 Data
+  );
+
+VOID
+WriteIo16 (
+  IN       UINT16 Address,
+  IN       UINT16 Data
+  );
+
+VOID
+WriteIo32 (
+  IN       UINT16 Address,
+  IN       UINT32 Data
+  );
+
+UINT8
+Read64Mem8 (
+  IN       UINT64 Address
+  );
+
+UINT16
+Read64Mem16 (
+  IN       UINT64 Address
+  );
+
+UINT32
+Read64Mem32 (
+  IN       UINT64 Address
+  );
+
+VOID
+Write64Mem8 (
+  IN       UINT64 Address,
+  IN       UINT8 Data
+  );
+
+VOID
+Write64Mem16 (
+  IN       UINT64 Address,
+  IN       UINT16 Data
+  );
+
+VOID
+Write64Mem32 (
+  IN       UINT64 Address,
+  IN       UINT32 Data
+  );
+
+UINT64
+ReadTSC (
+  void
+  );
+
+// MSR
+VOID
+LibAmdMsrRead (
+  IN       UINT32 MsrAddress,
+     OUT   UINT64 *Value,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+LibAmdMsrWrite (
+  IN       UINT32 MsrAddress,
+  IN       UINT64 *Value,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+// IO
+VOID
+LibAmdIoRead (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       UINT16 IoAddress,
+     OUT   VOID *Value,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+LibAmdIoWrite (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       UINT16 IoAddress,
+  IN       CONST VOID *Value,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+LibAmdIoRMW (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       UINT16 IoAddress,
+  IN       CONST VOID *Data,
+  IN       CONST VOID *DataMask,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+LibAmdIoPoll (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       UINT16 IoAddress,
+  IN       CONST VOID *Data,
+  IN       CONST VOID *DataMask,
+  IN       UINT64 Delay,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+// Memory or MMIO
+VOID
+LibAmdMemRead (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       UINT64 MemAddress,
+     OUT   VOID *Value,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+LibAmdMemWrite (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       UINT64 MemAddress,
+  IN       CONST VOID *Value,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+LibAmdMemRMW (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       UINT64 MemAddress,
+  IN       CONST VOID *Data,
+  IN       CONST VOID *DataMask,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+LibAmdMemPoll (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       UINT64 MemAddress,
+  IN       CONST VOID *Data,
+  IN       CONST VOID *DataMask,
+  IN       UINT64 Delay,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+// PCI
+VOID
+LibAmdPciRead (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR PciAddress,
+     OUT   VOID *Value,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+LibAmdPciWrite (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR PciAddress,
+  IN       CONST VOID *Value,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+LibAmdPciRMW (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR PciAddress,
+  IN       CONST VOID *Data,
+  IN       CONST VOID *DataMask,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+LibAmdPciPoll (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR PciAddress,
+  IN       CONST VOID *Data,
+  IN       CONST VOID *DataMask,
+  IN       UINT64 Delay,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+LibAmdPciReadBits (
+  IN       PCI_ADDR Address,
+  IN       UINT8 Highbit,
+  IN       UINT8 Lowbit,
+     OUT   UINT32 *Value,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+LibAmdPciWriteBits (
+  IN       PCI_ADDR Address,
+  IN       UINT8 Highbit,
+  IN       UINT8 Lowbit,
+  IN       CONST UINT32 *Value,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+LibAmdPciFindNextCap (
+  IN OUT   PCI_ADDR *Address,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+// CPUID
+VOID
+LibAmdCpuidRead (
+  IN       UINT32 CpuidFcnAddress,
+     OUT   CPUID_DATA *Value,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+// Utility Functions
+VOID
+LibAmdMemFill (
+  IN       VOID *Destination,
+  IN       UINT8 Value,
+  IN       UINTN FillLength,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+LibAmdMemCopy (
+  IN       VOID *Destination,
+  IN       CONST VOID *Source,
+  IN       UINTN CopyLength,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+CONST VOID *
+LibAmdLocateImage (
+  IN       CONST VOID *StartAddress,
+  IN       CONST VOID *EndAddress,
+  IN       UINT32 Alignment,
+  IN       CONST CHAR8 ModuleSignature[8]
+  );
+
+UINT32
+LibAmdGetPackageType (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+BOOLEAN
+LibAmdVerifyImageChecksum (
+  IN       CONST VOID *ImagePtr
+  );
+
+UINT8
+LibAmdBitScanReverse (
+  IN       UINT32 value
+  );
+UINT8
+LibAmdBitScanForward (
+  IN       UINT32 value
+  );
+
+VOID
+LibAmdReadCpuReg (
+  IN       UINT8 RegNum,
+     OUT   UINT32 *Value
+  );
+VOID
+LibAmdWriteCpuReg (
+  IN       UINT8 RegNum,
+  IN       UINT32 Value
+  );
+
+VOID
+LibAmdWriteBackInvalidateCache (
+  void
+  );
+
+VOID
+LibAmdSimNowEnterDebugger (
+  void
+  );
+
+VOID
+LibAmdHDTBreakPoint (
+  void
+  );
+
+UINT8
+LibAmdAccessWidth (
+  IN       ACCESS_WIDTH AccessWidth
+  );
+
+VOID
+LibAmdCLFlush (
+  IN       UINT64 Address,
+  IN       UINT8  Count
+  );
+
+VOID
+StopHere (
+  void
+  );
+
+VOID
+LibAmdFinit (
+  void
+  );
+
+VOID
+LibAmdFnclex (
+  void
+  );
+
+VOID
+LibAmdReadMxcsr (
+     OUT   UINT32 *Value
+  );
+
+VOID
+LibAmdWriteMxcsr (
+  IN       UINT32 *Value
+  );
+
+#endif // _AMD_LIB_H_

src/vendorcode/amd/pi/00630F01/Makefile.inc

@@ -0,0 +1,122 @@
+#*****************************************************************************
+#
+# Copyright (c) 2012,        Advanced Micro Devices, Inc.
+#               2013 - 2014, Sage Electronic Engineering, LLC
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#     * Redistributions of source code must retain the above copyright
+#       notice, this list of conditions and the following disclaimer.
+#     * Redistributions in binary form must reproduce the above copyright
+#       notice, this list of conditions and the following disclaimer in the
+#       documentation and/or other materials provided with the distribution.
+#     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+#       its contributors may be used to endorse or promote products derived
+#       from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+#*****************************************************************************
+
+# AGESA V5 Files
+AGESA_ROOT = $(call strip_quotes,$(src)/../$(CONFIG_AGESA_BINARY_PI_PATH))
+
+AGESA_INC = -I$(obj)
+
+AGESA_INC += -I$(src)/mainboard/$(MAINBOARDDIR)
+AGESA_INC += -I$(AGESA_ROOT)/binaryPI
+AGESA_INC += -I$(AGESA_ROOT)
+AGESA_INC += -I$(AGESA_ROOT)/Include
+AGESA_INC += -I$(src)/vendorcode/amd/pi/00630F01
+AGESA_INC += -I$(src)/vendorcode/amd/pi/00630F01/Lib
+AGESA_INC += -I$(AGESA_ROOT)/Proc
+AGESA_INC += -I$(AGESA_ROOT)/Proc/Common
+AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU
+AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU/Family
+AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU/Feature
+AGESA_INC += -I$(AGESA_ROOT)/Proc/Fch
+AGESA_INC += -I$(AGESA_ROOT)/Proc/Fch/Common
+AGESA_INC += -I$(AGESA_ROOT)/Proc/IDS
+
+AGESA_INC += -I$(src)/southbridge/amd/pi/hudson
+
+AGESA_INC += -I$(src)/arch/x86/include
+AGESA_INC += -I$(src)/include
+
+AGESA_CFLAGS += -march=amdfam10 -mno-3dnow -fno-zero-initialized-in-bss -fno-strict-aliasing
+CFLAGS_x86_32 += $(AGESA_CFLAGS)
+
+export AGESA_ROOT := $(AGESA_ROOT)
+export AGESA_INC  := $(AGESA_INC)
+export AGESA_CFLAGS  := $(AGESA_CFLAGS)
+
+CC_bootblock := $(CC_bootblock) $(AGESA_INC) $(AGESA_CFLAGS)
+CC_romstage := $(CC_romstage) $(AGESA_INC) $(AGESA_CFLAGS)
+CC_ramstage := $(CC_ramstage) $(AGESA_INC) $(AGESA_CFLAGS)
+CC_x86_32 := $(CC_x86_32) $(AGESA_INC) $(AGESA_CFLAGS)
+
+#######################################################################
+
+define create_agesa_cp_template
+
+# $1 AGESA source file
+# $2 AGESA copy-to location
+$(agesa_src_path)/$(notdir $2): $2 $(agesa_src_path)
+	@printf "    AGESA      Copying $$(notdir $2) => $$(@D)\n"
+	if [ ! -r $(agesa_src_path)/$(notdir $2) ]; then                   \
+		cp -uf $2 $$(@D);                                                     \
+	fi
+
+$(agesa_obj_path)/$1.libagesa.o: $(agesa_src_path)/$(notdir $2) $(obj)/config.h $(src)/include/kconfig.h $(agesa_obj_path)
+	@printf "    CC         $(subst $(agesa_obj_path)/,,$$(@))\n"
+	$(CC_libagesa) -c -MMD $(CFLAGS_libagesa) $(AGESA_CFLAGS)                 \
+	               $(AGESA_INC)                                               \
+	               -include $(obj)/config.h -include $(src)/include/kconfig.h \
+	               -o $$@                                                     \
+	               $(agesa_src_path)/$(notdir $2)
+
+endef
+
+agesa_raw_files += $(wildcard $(src)/vendorcode/amd/pi/00630F01/Lib/*.[cS])
+agesa_raw_files += $(wildcard $(AGESA_ROOT)/binaryPI/*.[cS])
+
+classes-$(CONFIG_CPU_AMD_AGESA_BINARY_PI) += libagesa
+$(eval $(call create_class_compiler,libagesa,x86_32))
+
+agesa_src_files := $(strip $(sort $(foreach file,$(strip $(agesa_raw_files)),$(call strip_quotes,$(file)))))
+agesa_obj_path := $(strip $(obj)/vendorcode/amd)
+agesa_src_path := $(strip $(obj)/agesa)
+agesa_src_copies := $(strip $(foreach file,$(agesa_src_files),$(agesa_obj_path)/$(notdir $(file))))
+agesa_obj_copies := $(strip $(agesa_src_copies:.c=.libagesa.o))
+
+$(agesa_src_path):
+	mkdir -p $@
+
+$(agesa_obj_path):
+	mkdir -p $@
+
+$(foreach file,$(strip $(agesa_src_files)),$(eval $(call create_agesa_cp_template,$(basename $(notdir $(file))),$(file))))
+
+$(obj)/agesa/libagesa.00630F01.a: $(agesa_obj_copies)
+	@printf "    AGESA      $(subst $(agesa_obj_path)/,,$(@))\n"
+	ar rcs $@ $+
+
+romstage-libs += $(obj)/agesa/libagesa.00630F01.a
+ramstage-libs += $(obj)/agesa/libagesa.00630F01.a
+
+#######################################################################
+
+cbfs-files-$(CONFIG_CPU_AMD_AGESA_BINARY_PI) += AGESA
+AGESA-file := $(CONFIG_AGESA_BINARY_PI_PATH)/$(CONFIG_AGESA_BINARY_PI_FILE)
+AGESA-type := raw
+AGESA-position := $(CONFIG_AGESA_BINARY_PI_LOCATION)

src/vendorcode/amd/pi/Kconfig

@@ -1 +1,2 @@
+source src/vendorcode/amd/pi/00630F01/Kconfig
 source src/vendorcode/amd/pi/00730F01/Kconfig

src/vendorcode/amd/pi/Makefile.inc

@@ -1 +1,2 @@
 subdirs-$(CONFIG_CPU_AMD_PI_00730F01) += 00730F01
+subdirs-$(CONFIG_CPU_AMD_PI_00630F01) += 00630F01