From 98e827ea746fa45c37450a34377739e3b5046fb6 Mon Sep 17 00:00:00 2001
From: Meera Ravindranath <meera.ravindranath@intel.com>
Date: Wed, 17 Nov 2021 18:11:14 +0530
Subject: [PATCH] mb/intel/adlrvp: Enable CPU PCIe RP 2

Disabling CPU PCIe RP 2 (commit:3fd39467b Fix S0ix regression)
causes regression in NVMe boot on ADL-P RVP boards.

Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I0b8b76a5537d8b80777cb7588ce6b22281af7882
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59392
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/intel/adlrvp/devicetree.cb | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb
index 8926887c33..2c45e85e34 100644
--- a/src/mainboard/intel/adlrvp/devicetree.cb
+++ b/src/mainboard/intel/adlrvp/devicetree.cb
@@ -83,6 +83,12 @@ chip soc/intel/alderlake
 		.clk_src = 0,
 	}"
 
+	# Enable CPU PCIE RP 2 using CLK 3
+	register "cpu_pcie_rp[CPU_RP(2)]" = "{
+		.clk_req = 3,
+		.clk_src = 3,
+	}"
+
 	# Enable CPU PCIE RP 3 using CLK 4
 	register "cpu_pcie_rp[CPU_RP(3)]" = "{
 		.clk_req = 4,