From 98f43a1f757a89afa4e48d15ff48abdd7e62f46b Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Mon, 5 Aug 2019 16:18:56 -0600 Subject: [PATCH] cpu/x86 mp_init: Add option for AMD INIT SIPI sequence The common code adheres to the Intel requirement of bringing up the cores with INIT SIPI SIPI. This sequence is tolerated on some AMD AMD CPUs but fails on others. Add a way to skip the second SIPI. TEST=Mock up on grunt and verify no errors BUG=b:138919564 Change-Id: I201869003ddc7d04d332cd5734ac6d63979d89e0 Signed-off-by: Marshall Dawson Reviewed-on: https://review.coreboot.org/c/coreboot/+/34759 Reviewed-by: Martin Roth Tested-by: build bot (Jenkins) --- src/cpu/x86/Kconfig | 8 ++++++++ src/cpu/x86/mp_init.c | 3 +++ 2 files changed, 11 insertions(+) diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index caee5dbd10..a8cf54d89e 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -155,6 +155,14 @@ config X86_AMD_FIXED_MTRRS This option informs the MTRR code to use the RdMem and WrMem fields in the fixed MTRR MSRs. +config X86_AMD_INIT_SIPI + bool + default n + help + This option limits the number of SIPI signals sent during during the + common AP setup. Intel documentation specifies an INIT SIPI SIPI + sequence, however this doesn't work on some AMD platforms. + config MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING def_bool n help diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index dbaf73fdfb..3658a5b698 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -482,6 +482,9 @@ static int start_aps(struct bus *cpu_bus, int ap_count, atomic_t *num_aps) /* Wait for CPUs to check in up to 200 us. */ wait_for_aps(num_aps, ap_count, 200 /* us */, 15 /* us */); + if (CONFIG(X86_AMD_INIT_SIPI)) + return 0; + /* Send 2nd SIPI */ if ((lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY)) { printk(BIOS_DEBUG, "Waiting for ICR not to be busy...");