soc/intel/cannonlake: Allow coreboot to handle required chipset lockdown
This patch disables FSP-S chipset lockdown UPDs and lets coreboot perform chipset lockdown in ramstage. BUG=b:138200201 TEST=FSP debug build suggests those UPDs are disable now. Change-Id: I7e53c4e4987a7b0e7f475c92b0f797d94fdd60f4 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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@ -19,6 +19,7 @@
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#include <fsp/api.h>
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#include <fsp/util.h>
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#include <intelblocks/xdci.h>
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#include <intelpch/lockdown.h>
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#include <soc/intel/common/vbt.h>
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#include <soc/pci_devs.h>
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#include <soc/ramstage.h>
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@ -402,6 +403,39 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
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configure_gspi_cs(i, config,
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¶ms->SerialIoSpiCsPolarity[0], NULL, NULL);
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#endif
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/* Chipset Lockdown */
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if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) {
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tconfig->PchLockDownGlobalSmi = 0;
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tconfig->PchLockDownBiosInterface = 0;
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params->PchLockDownBiosLock = 0;
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params->PchLockDownRtcMemoryLock = 0;
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/*
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* TODO: Disable SpiFlashCfgLockDown config after FSP provides
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* dedicated UPD
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*
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* Skip SPI Flash Lockdown from inside FSP.
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* Making this config "0" means FSP won't set the FLOCKDN bit
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* of SPIBAR + 0x04 (i.e., Bit 15 of BIOS_HSFSTS_CTL).
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* So, it becomes coreboot's responsibility to set this bit
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* before end of POST for security concerns.
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*/
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// params->SpiFlashCfgLockDown = 0;
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} else {
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tconfig->PchLockDownGlobalSmi = 1;
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tconfig->PchLockDownBiosInterface = 1;
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params->PchLockDownBiosLock = 1;
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params->PchLockDownRtcMemoryLock = 1;
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/*
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* TODO: Enable SpiFlashCfgLockDown config after FSP provides
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* dedicated UPD
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*
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* Enable SPI Flash Lockdown from inside FSP.
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* Making this config "1" means FSP will set the FLOCKDN bit
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* of SPIBAR + 0x04 (i.e., Bit 15 of BIOS_HSFSTS_CTL).
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*/
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// params->SpiFlashCfgLockDown = 1;
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}
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}
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/* Mainboard GPIO Configuration */
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