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soc/intel/alderlake: Update CPU microcode patch base address/size 

This patch updates CPU microcode patch base address/size to FSP-S
UPD to have second microcode patch loaded successfully to enable
Mcheck flow.

This is new feature requirement for ADL as per new Mcheck initialization
flow.

BUG=b:176551651
TEST=Able to reach beyond PC6 without any MCE.

Change-Id: I936816e3173dbcdf82b2b16b465f6b4ed5d90335
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48847
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik 2020-12-22 10:54:44 +05:30
parent 12defa9ee7
commit 99289a89a3
1 changed files with 11 additions and 0 deletions
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11
src/soc/intel/alderlake/fsp_params.c
View File

@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <assert.h>
#include <cbfs.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
@ -89,6 +90,8 @@ __weak void mainboard_update_soc_chip_config(struct soc_intel_alderlake_config *
void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
{
int i;
const struct microcode *microcode_file;
size_t microcode_len;
FSP_S_CONFIG *params = &supd->FspsConfig;
struct device *dev;
@ -99,6 +102,14 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
/* Parse device tree and enable/disable Serial I/O devices */
parse_devicetree(params);
microcode_file = cbfs_map("cpu_microcode_blob.bin", &microcode_len);
if ((microcode_file != NULL) && (microcode_len != 0)) {
/* Update CPU Microcode patch base address/size */
params->MicrocodeRegionBase = (uint32_t)microcode_file;
params->MicrocodeRegionSize = (uint32_t)microcode_len;
}
/* Load VBT before devicetree-specific config. */
params->GraphicsConfigPtr = (uintptr_t)vbt_get();