FUI: add intel_dp driver derived from kernel functions
These functions are not all used yet, but do compile and are partially used in the FUI testing. They were extracted from the 3.4 kernel using coccinnelle filters. The .c files are only compiled in if CONFIG_INTEL_DP is set. Change-Id: Id95622a75aa02b496c9ea4717cb143394a8332e3 Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/60245 Commit-Queue: Ronald G. Minnich <rminnich@chromium.org> Tested-by: Ronald G. Minnich <rminnich@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/4329 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Ronald G. Minnich
Ronald G. Minnich
parent
5bcca7e982
commit
99451b174a
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@ -24,6 +24,7 @@ source src/drivers/emulation/Kconfig
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source src/drivers/generic/Kconfig
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source src/drivers/generic/Kconfig
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source src/drivers/i2c/Kconfig
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source src/drivers/i2c/Kconfig
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source src/drivers/ics/Kconfig
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source src/drivers/ics/Kconfig
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source src/drivers/intel/Kconfig
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source src/drivers/ipmi/Kconfig
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source src/drivers/ipmi/Kconfig
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source src/drivers/maxim/Kconfig
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source src/drivers/maxim/Kconfig
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source src/drivers/oxford/Kconfig
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source src/drivers/oxford/Kconfig
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@ -0,0 +1,20 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2013 Google Inc.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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source src/drivers/intel/gma/Kconfig
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@ -0,0 +1,24 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright 2013 Google Inc.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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config INTEL_DP
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bool
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default n
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help
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helper functions for intel display port operations
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@ -0,0 +1,21 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2013 Google Inc.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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ramstage-$(CONFIG_INTEL_DP) += intel_dp.c drm_dp_helper.c
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@ -0,0 +1,119 @@
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/*
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* Copyright 2013 Google Inc.
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* Copyright © 2009 Keith Packard
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*
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* Permission to use, copy, modify, distribute, and sell this software and its
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* documentation for any purpose is hereby granted without fee, provided that
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* the above copyright notice appear in all copies and that both that copyright
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* notice and this permission notice appear in supporting documentation, and
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* that the name of the copyright holders not be used in advertising or
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* publicity pertaining to distribution of the software without specific,
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* written prior permission. The copyright holders make no representations
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* about the suitability of this software for any purpose. It is provided "as
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* is" without express or implied warranty.
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*
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* THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
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* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
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* EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
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* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
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* DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
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* OF THIS SOFTWARE.
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*/
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#include <console/console.h>
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#include <stdint.h>
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#include <delay.h>
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#include <drivers/intel/gma/i915.h>
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#include <string.h>
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#include <edid.h>
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/* reduced a lot for coreboot. */
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/**
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* DOC: dp helpers
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*
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* These functions contain some common logic and helpers at various
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* abstraction levels to deal with Display Port sink devices and
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* related things like DP aux channel transfers, EDID reading over DP
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* aux channels, decoding certain DPCD blocks, ...
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*/
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/* Helpers for DP link training */
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static u8 dp_link_status(u8 link_status[DP_LINK_STATUS_SIZE], int r)
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{
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printk(BIOS_SPEW, "%s: %d, %d, %d\n", __func__,
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r, r - DP_LANE0_1_STATUS,
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link_status[r - DP_LANE0_1_STATUS]);
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return link_status[r - DP_LANE0_1_STATUS];
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}
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static u8 dp_get_lane_status(u8 link_status[DP_LINK_STATUS_SIZE],
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int lane)
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{
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int i = DP_LANE0_1_STATUS + (lane >> 1);
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int s = (lane & 1) * 4;
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u8 l = dp_link_status(link_status, i);
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return (l >> s) & 0xf;
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}
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int drm_dp_channel_eq_ok(u8 link_status[DP_LINK_STATUS_SIZE],
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int lane_count)
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{
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u8 lane_align;
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u8 lane_status;
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int lane;
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lane_align = dp_link_status(link_status,
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DP_LANE_ALIGN_STATUS_UPDATED);
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if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
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return 0;
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for (lane = 0; lane < lane_count; lane++) {
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lane_status = dp_get_lane_status(link_status, lane);
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if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS)
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return 0;
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}
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return 1;
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}
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int drm_dp_clock_recovery_ok(u8 link_status[DP_LINK_STATUS_SIZE],
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int lane_count)
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{
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int lane;
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u8 lane_status;
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for (lane = 0; lane < lane_count; lane++) {
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lane_status = dp_get_lane_status(link_status, lane);
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if ((lane_status & DP_LANE_CR_DONE) == 0)
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return 0;
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}
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return 1;
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}
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u8 drm_dp_get_adjust_request_voltage(u8 link_status[DP_LINK_STATUS_SIZE],
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int lane)
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{
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int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
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int s = ((lane & 1) ?
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DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
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DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
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u8 l = dp_link_status(link_status, i);
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printk(BIOS_SPEW, "%s: i %d s %d l %d return %d\n",
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__func__, i, s, l,
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((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT);
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return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
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}
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u8 drm_dp_get_adjust_request_pre_emphasis(u8 link_status[DP_LINK_STATUS_SIZE],
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int lane)
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{
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int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
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int s = ((lane & 1) ?
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DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
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DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
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u8 l = dp_link_status(link_status, i);
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return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
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}
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@ -0,0 +1,239 @@
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/*
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* Copyright 2013 Google Inc.
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* Copyright © 2008 Keith Packard
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*
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* Permission to use, copy, modify, distribute, and sell this software and its
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* documentation for any purpose is hereby granted without fee, provided that
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* the above copyright notice appear in all copies and that both that copyright
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* notice and this permission notice appear in supporting documentation, and
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* that the name of the copyright holders not be used in advertising or
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* publicity pertaining to distribution of the software without specific,
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* written prior permission. The copyright holders make no representations
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* about the suitability of this software for any purpose. It is provided "as
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* is" without express or implied warranty.
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*
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* THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
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* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
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* EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
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* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
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* DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
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* OF THIS SOFTWARE.
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*/
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#ifndef _DRM_DP_HELPER_H_
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#define _DRM_DP_HELPER_H_
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/* From the VESA DisplayPort spec */
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#define AUX_NATIVE_WRITE 0x8
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#define AUX_NATIVE_READ 0x9
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#define AUX_I2C_WRITE 0x0
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#define AUX_I2C_READ 0x1
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#define AUX_I2C_STATUS 0x2
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#define AUX_I2C_MOT 0x4
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#define AUX_NATIVE_REPLY_ACK (0x0 << 4)
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#define AUX_NATIVE_REPLY_NACK (0x1 << 4)
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#define AUX_NATIVE_REPLY_DEFER (0x2 << 4)
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#define AUX_NATIVE_REPLY_MASK (0x3 << 4)
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#define AUX_I2C_REPLY_ACK (0x0 << 6)
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#define AUX_I2C_REPLY_NACK (0x1 << 6)
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#define AUX_I2C_REPLY_DEFER (0x2 << 6)
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#define AUX_I2C_REPLY_MASK (0x3 << 6)
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/* AUX CH addresses */
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/* DPCD */
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#define DP_DPCD_REV 0x000
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#define DP_MAX_LINK_RATE 0x001
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#define DP_MAX_LANE_COUNT 0x002
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# define DP_MAX_LANE_COUNT_MASK 0x1f
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# define DP_TPS3_SUPPORTED (1 << 6)
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# define DP_ENHANCED_FRAME_CAP (1 << 7)
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#define DP_MAX_DOWNSPREAD 0x003
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# define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6)
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#define DP_NORP 0x004
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#define DP_DOWNSTREAMPORT_PRESENT 0x005
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# define DP_DWN_STRM_PORT_PRESENT (1 << 0)
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# define DP_DWN_STRM_PORT_TYPE_MASK 0x06
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/* 00b = DisplayPort */
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/* 01b = Analog */
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/* 10b = TMDS or HDMI */
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/* 11b = Other */
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# define DP_FORMAT_CONVERSION (1 << 3)
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#define DP_MAIN_LINK_CHANNEL_CODING 0x006
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#define DP_EDP_CONFIGURATION_CAP 0x00d
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#define DP_TRAINING_AUX_RD_INTERVAL 0x00e
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#define DP_PSR_SUPPORT 0x070
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# define DP_PSR_IS_SUPPORTED 1
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#define DP_PSR_CAPS 0x071
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# define DP_PSR_NO_TRAIN_ON_EXIT 1
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# define DP_PSR_SETUP_TIME_330 (0 << 1)
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# define DP_PSR_SETUP_TIME_275 (1 << 1)
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# define DP_PSR_SETUP_TIME_220 (2 << 1)
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# define DP_PSR_SETUP_TIME_165 (3 << 1)
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# define DP_PSR_SETUP_TIME_110 (4 << 1)
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# define DP_PSR_SETUP_TIME_55 (5 << 1)
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# define DP_PSR_SETUP_TIME_0 (6 << 1)
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# define DP_PSR_SETUP_TIME_MASK (7 << 1)
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# define DP_PSR_SETUP_TIME_SHIFT 1
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/* link configuration */
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#define DP_LINK_BW_SET 0x100
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# define DP_LINK_BW_1_62 0x06
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# define DP_LINK_BW_2_7 0x0a
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# define DP_LINK_BW_5_4 0x14
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#define DP_LANE_COUNT_SET 0x101
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# define DP_LANE_COUNT_MASK 0x0f
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# define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7)
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#define DP_TRAINING_PATTERN_SET 0x102
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# define DP_TRAINING_PATTERN_DISABLE 0
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# define DP_TRAINING_PATTERN_1 1
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# define DP_TRAINING_PATTERN_2 2
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# define DP_TRAINING_PATTERN_3 3
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# define DP_TRAINING_PATTERN_MASK 0x3
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# define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2)
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# define DP_LINK_QUAL_PATTERN_D10_2 (1 << 2)
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# define DP_LINK_QUAL_PATTERN_ERROR_RATE (2 << 2)
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# define DP_LINK_QUAL_PATTERN_PRBS7 (3 << 2)
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# define DP_LINK_QUAL_PATTERN_MASK (3 << 2)
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# define DP_RECOVERED_CLOCK_OUT_EN (1 << 4)
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# define DP_LINK_SCRAMBLING_DISABLE (1 << 5)
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# define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6)
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# define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6)
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# define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6)
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# define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6)
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#define DP_TRAINING_LANE0_SET 0x103
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#define DP_TRAINING_LANE1_SET 0x104
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#define DP_TRAINING_LANE2_SET 0x105
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#define DP_TRAINING_LANE3_SET 0x106
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# define DP_TRAIN_VOLTAGE_SWING_MASK 0x3
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# define DP_TRAIN_VOLTAGE_SWING_SHIFT 0
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# define DP_TRAIN_MAX_SWING_REACHED (1 << 2)
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# define DP_TRAIN_VOLTAGE_SWING_400 (0 << 0)
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# define DP_TRAIN_VOLTAGE_SWING_600 (1 << 0)
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# define DP_TRAIN_VOLTAGE_SWING_800 (2 << 0)
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# define DP_TRAIN_VOLTAGE_SWING_1200 (3 << 0)
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# define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3)
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# define DP_TRAIN_PRE_EMPHASIS_0 (0 << 3)
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# define DP_TRAIN_PRE_EMPHASIS_3_5 (1 << 3)
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# define DP_TRAIN_PRE_EMPHASIS_6 (2 << 3)
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# define DP_TRAIN_PRE_EMPHASIS_9_5 (3 << 3)
|
||||||
|
|
||||||
|
# define DP_TRAIN_PRE_EMPHASIS_SHIFT 3
|
||||||
|
# define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5)
|
||||||
|
|
||||||
|
#define DP_DOWNSPREAD_CTRL 0x107
|
||||||
|
# define DP_SPREAD_AMP_0_5 (1 << 4)
|
||||||
|
|
||||||
|
#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108
|
||||||
|
# define DP_SET_ANSI_8B10B (1 << 0)
|
||||||
|
|
||||||
|
#define DP_PSR_EN_CFG 0x170
|
||||||
|
# define DP_PSR_ENABLE (1 << 0)
|
||||||
|
# define DP_PSR_MAIN_LINK_ACTIVE (1 << 1)
|
||||||
|
# define DP_PSR_CRC_VERIFICATION (1 << 2)
|
||||||
|
# define DP_PSR_FRAME_CAPTURE (1 << 3)
|
||||||
|
|
||||||
|
#define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201
|
||||||
|
# define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0)
|
||||||
|
# define DP_AUTOMATED_TEST_REQUEST (1 << 1)
|
||||||
|
# define DP_CP_IRQ (1 << 2)
|
||||||
|
# define DP_SINK_SPECIFIC_IRQ (1 << 6)
|
||||||
|
|
||||||
|
#define DP_EDP_CONFIGURATION_SET 0x10a
|
||||||
|
|
||||||
|
#define DP_LANE0_1_STATUS 0x202
|
||||||
|
#define DP_LANE2_3_STATUS 0x203
|
||||||
|
# define DP_LANE_CR_DONE (1 << 0)
|
||||||
|
# define DP_LANE_CHANNEL_EQ_DONE (1 << 1)
|
||||||
|
# define DP_LANE_SYMBOL_LOCKED (1 << 2)
|
||||||
|
|
||||||
|
#define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \
|
||||||
|
DP_LANE_CHANNEL_EQ_DONE | \
|
||||||
|
DP_LANE_SYMBOL_LOCKED)
|
||||||
|
|
||||||
|
#define DP_LANE_ALIGN_STATUS_UPDATED 0x204
|
||||||
|
|
||||||
|
#define DP_INTERLANE_ALIGN_DONE (1 << 0)
|
||||||
|
#define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6)
|
||||||
|
#define DP_LINK_STATUS_UPDATED (1 << 7)
|
||||||
|
|
||||||
|
#define DP_SINK_STATUS 0x205
|
||||||
|
|
||||||
|
#define DP_RECEIVE_PORT_0_STATUS (1 << 0)
|
||||||
|
#define DP_RECEIVE_PORT_1_STATUS (1 << 1)
|
||||||
|
|
||||||
|
#define DP_ADJUST_REQUEST_LANE0_1 0x206
|
||||||
|
#define DP_ADJUST_REQUEST_LANE2_3 0x207
|
||||||
|
# define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03
|
||||||
|
# define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0
|
||||||
|
# define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c
|
||||||
|
# define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2
|
||||||
|
# define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30
|
||||||
|
# define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4
|
||||||
|
# define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0
|
||||||
|
# define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6
|
||||||
|
|
||||||
|
#define DP_TEST_REQUEST 0x218
|
||||||
|
# define DP_TEST_LINK_TRAINING (1 << 0)
|
||||||
|
# define DP_TEST_LINK_PATTERN (1 << 1)
|
||||||
|
# define DP_TEST_LINK_EDID_READ (1 << 2)
|
||||||
|
# define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */
|
||||||
|
|
||||||
|
#define DP_TEST_LINK_RATE 0x219
|
||||||
|
# define DP_LINK_RATE_162 (0x6)
|
||||||
|
# define DP_LINK_RATE_27 (0xa)
|
||||||
|
|
||||||
|
#define DP_TEST_LANE_COUNT 0x220
|
||||||
|
|
||||||
|
#define DP_TEST_PATTERN 0x221
|
||||||
|
|
||||||
|
#define DP_TEST_RESPONSE 0x260
|
||||||
|
# define DP_TEST_ACK (1 << 0)
|
||||||
|
# define DP_TEST_NAK (1 << 1)
|
||||||
|
# define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2)
|
||||||
|
|
||||||
|
#define DP_SET_POWER 0x600
|
||||||
|
# define DP_SET_POWER_D0 0x1
|
||||||
|
# define DP_SET_POWER_D3 0x2
|
||||||
|
|
||||||
|
#define DP_PSR_ERROR_STATUS 0x2006
|
||||||
|
# define DP_PSR_LINK_CRC_ERROR (1 << 0)
|
||||||
|
# define DP_PSR_RFB_STORAGE_ERROR (1 << 1)
|
||||||
|
|
||||||
|
#define DP_PSR_ESI 0x2007
|
||||||
|
# define DP_PSR_CAPS_CHANGE (1 << 0)
|
||||||
|
|
||||||
|
#define DP_PSR_STATUS 0x2008
|
||||||
|
# define DP_PSR_SINK_INACTIVE 0
|
||||||
|
# define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1
|
||||||
|
# define DP_PSR_SINK_ACTIVE_RFB 2
|
||||||
|
# define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3
|
||||||
|
# define DP_PSR_SINK_ACTIVE_RESYNC 4
|
||||||
|
# define DP_PSR_SINK_INTERNAL_ERROR 7
|
||||||
|
# define DP_PSR_SINK_STATE_MASK 0x07
|
||||||
|
|
||||||
|
#define MODE_I2C_START 1
|
||||||
|
#define MODE_I2C_WRITE 2
|
||||||
|
#define MODE_I2C_READ 4
|
||||||
|
#define MODE_I2C_STOP 8
|
||||||
|
|
||||||
|
#endif /* _DRM_DP_HELPER_H_ */
|
||||||
|
|
@ -0,0 +1,180 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the coreboot project.
|
||||||
|
*
|
||||||
|
* Copyright 2012 Google Inc.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; version 2 of the License.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <drivers/intel/gma/i915_reg.h>
|
||||||
|
#include <drivers/intel/gma/drm_dp_helper.h>
|
||||||
|
#include <edid.h>
|
||||||
|
|
||||||
|
/* port types. We stick with the same defines as the kernel */
|
||||||
|
#define INTEL_OUTPUT_UNUSED 0
|
||||||
|
#define INTEL_OUTPUT_ANALOG 1
|
||||||
|
#define INTEL_OUTPUT_DVO 2
|
||||||
|
#define INTEL_OUTPUT_SDVO 3
|
||||||
|
#define INTEL_OUTPUT_LVDS 4
|
||||||
|
#define INTEL_OUTPUT_TVOUT 5
|
||||||
|
#define INTEL_OUTPUT_HDMI 6
|
||||||
|
#define INTEL_OUTPUT_DISPLAYPORT 7
|
||||||
|
#define INTEL_OUTPUT_EDP 8
|
||||||
|
|
||||||
|
/* things that are, strangely, not defined anywhere? */
|
||||||
|
#define PCH_PP_UNLOCK 0xabcd0000
|
||||||
|
#define WMx_LP_SR_EN (1<<31)
|
||||||
|
#define PRB0_TAIL 0x02030
|
||||||
|
#define PRB0_HEAD 0x02034
|
||||||
|
#define PRB0_START 0x02038
|
||||||
|
#define PRB0_CTL 0x0203c
|
||||||
|
|
||||||
|
/* debug enums. These are for printks that, due to their place in the
|
||||||
|
* middle of graphics device IO, might change timing. Use with care
|
||||||
|
* or not at all.
|
||||||
|
*/
|
||||||
|
enum {
|
||||||
|
vio = 2, /* dump every IO */
|
||||||
|
vspin = 4, /* print # of times we spun on a register value */
|
||||||
|
};
|
||||||
|
|
||||||
|
/* The mainboard must provide these functions. */
|
||||||
|
unsigned long io_i915_read32(unsigned long addr);
|
||||||
|
void io_i915_write32(unsigned long val, unsigned long addr);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* To communicate to and control the extracted-from-kernel code,
|
||||||
|
* we need this struct. It has a counterpart in the ARM code, so
|
||||||
|
* there is a precedent.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define DP_RECEIVER_CAP_SIZE 0xf
|
||||||
|
#define DP_LINK_STATUS_SIZE 6
|
||||||
|
#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
|
||||||
|
|
||||||
|
#define DP_LINK_CONFIGURATION_SIZE 9
|
||||||
|
|
||||||
|
struct intel_dp {
|
||||||
|
int gen; // 6 for link, 7 for wtm2
|
||||||
|
int has_pch_split; // 1 for link and wtm2
|
||||||
|
int has_pch_cpt; // 1 for everything we know about.
|
||||||
|
int is_haswell;
|
||||||
|
/* output register offset in MMIO space. Usually DP_A */
|
||||||
|
u32 output_reg;
|
||||||
|
/* The initial value of the DP register.
|
||||||
|
* Mainboards can set this to a non-zero
|
||||||
|
* value in the case that there are undetectable
|
||||||
|
* but essential parameters.
|
||||||
|
*/
|
||||||
|
u32 DP;
|
||||||
|
uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
|
||||||
|
u32 color_range;
|
||||||
|
/* these paramaters are determined after reading the DPCD */
|
||||||
|
int dpms_mode;
|
||||||
|
uint8_t link_bw;
|
||||||
|
uint8_t lane_count;
|
||||||
|
/* This data is read from the panel via the AUX channel.*/
|
||||||
|
uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
|
||||||
|
int type;
|
||||||
|
int edp;
|
||||||
|
int is_pch_edp;
|
||||||
|
/* state related to training. */
|
||||||
|
uint8_t train_set[4];
|
||||||
|
/* Determined from EDID or coreboot hard-sets. */
|
||||||
|
int panel_power_up_delay;
|
||||||
|
int panel_power_down_delay;
|
||||||
|
int panel_power_cycle_delay;
|
||||||
|
int backlight_on_delay;
|
||||||
|
int backlight_off_delay;
|
||||||
|
int want_panel_vdd;
|
||||||
|
u32 clock;
|
||||||
|
int port;
|
||||||
|
int pipe;
|
||||||
|
int bpp;
|
||||||
|
/* i2c on aux is ... interesting.
|
||||||
|
* Before you do an i2c cycle, you need to set the address.
|
||||||
|
* This requires we remember it from one moment to the next.
|
||||||
|
* Remember it here.
|
||||||
|
*/
|
||||||
|
u16 address;
|
||||||
|
/* timing parameters for aux channel IO. They used to compute these on
|
||||||
|
* each and every entry to the functions, which is kind of stupid, and it had
|
||||||
|
* errors anyway.
|
||||||
|
* note: you can get these from watching YABEL output. E.g.:
|
||||||
|
* you see an outb of 0x802300e1 to 64010. the 3 is the precharge
|
||||||
|
* and the e1 is the clock divider.
|
||||||
|
*/
|
||||||
|
u32 aux_clock_divider;
|
||||||
|
u32 precharge;
|
||||||
|
/* EDID, raw and processed */
|
||||||
|
u8 rawedid[256];
|
||||||
|
int edidlen;
|
||||||
|
struct edid edid;
|
||||||
|
/* computed values needed for "i915" registers */
|
||||||
|
int bytes_per_pixel;
|
||||||
|
u32 htotal;
|
||||||
|
u32 hblank;
|
||||||
|
u32 hsync;
|
||||||
|
u32 vtotal;
|
||||||
|
u32 vblank;
|
||||||
|
u32 vsync;
|
||||||
|
u32 pfa_sz;
|
||||||
|
u32 pfa_pos;
|
||||||
|
u32 pfa_ctl;
|
||||||
|
u32 pipesrc;
|
||||||
|
u32 stride;
|
||||||
|
};
|
||||||
|
|
||||||
|
/* we may yet need these. */
|
||||||
|
void intel_dp_mode_set(struct intel_dp *intel_dp);
|
||||||
|
void intel_dp_start_link_train(struct intel_dp *intel_dp);
|
||||||
|
void intel_dp_complete_link_train(struct intel_dp *intel_dp);
|
||||||
|
void intel_dp_link_down(struct intel_dp *intel_dp);
|
||||||
|
|
||||||
|
int intel_dp_i2c_init(struct intel_dp *intel_dp);
|
||||||
|
int intel_dp_i2c_aux_ch(struct intel_dp *intel_dp,
|
||||||
|
int mode, uint8_t write_byte, uint8_t *read_byte);
|
||||||
|
void
|
||||||
|
intel_dp_dpms(struct intel_dp *intel_dp, int mode);
|
||||||
|
|
||||||
|
int intel_dp_get_dpcd(struct intel_dp *intel_dp);
|
||||||
|
struct edid *intel_dp_get_edid(struct intel_dp *intel_dp);
|
||||||
|
|
||||||
|
void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
|
||||||
|
void ironlake_edp_pll_on(void);
|
||||||
|
void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
|
||||||
|
void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, int sync);
|
||||||
|
int intel_dp_get_max_downspread(struct intel_dp *intel_dp, u8 *max_downspread);
|
||||||
|
void ironlake_edp_panel_on(struct intel_dp *intel_dp);
|
||||||
|
void ironlake_edp_backlight_on(struct intel_dp *intel_dp);
|
||||||
|
/* needed only on haswell. */
|
||||||
|
void intel_prepare_ddi_buffers(int port, int use_fdi_mode);
|
||||||
|
void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, int port);
|
||||||
|
int intel_dp_aux_ch(struct intel_dp *intel_dp,
|
||||||
|
uint8_t *send, int send_bytes,
|
||||||
|
uint8_t *recv, int recv_size);
|
||||||
|
void unpack_aux(u32 src, uint8_t *dst, int dst_bytes);
|
||||||
|
|
||||||
|
|
||||||
|
/* drm_dp_helper.c */
|
||||||
|
int drm_dp_channel_eq_ok(u8 link_status[DP_LINK_STATUS_SIZE],
|
||||||
|
int lane_count);
|
||||||
|
int drm_dp_clock_recovery_ok(u8 link_status[DP_LINK_STATUS_SIZE],
|
||||||
|
int lane_count);
|
||||||
|
u8 drm_dp_get_adjust_request_voltage(u8 link_status[DP_LINK_STATUS_SIZE],
|
||||||
|
int lane);
|
||||||
|
u8 drm_dp_get_adjust_request_pre_emphasis(u8 link_status[DP_LINK_STATUS_SIZE],
|
||||||
|
int lane);
|
||||||
|
|
||||||
|
|
||||||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue