soc/intel/xeon_sp; Use soc specific stack-port function

Separate the get_stack_for_port into soc specific functions. This
removes a #if in common code.

Change-Id: Ib38a7d66947ded9b56193a9163e5128b2523e99c
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46971
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Marc Jones 2020-10-28 17:08:54 -06:00 committed by Marc Jones
parent 3dea2b63ee
commit 995a7e25a1
5 changed files with 53 additions and 43 deletions

View File

@ -26,5 +26,6 @@ int get_threads_per_package(void);
const struct SystemMemoryMapHob *get_system_memory_map(void);
void set_bios_init_completion(void);
int soc_get_stack_for_port(int port);
#endif /* _SOC_UTIL_H_ */

View File

@ -319,3 +319,25 @@ void set_bios_init_completion(void)
/* And finally, take care of the SBSP */
set_bios_init_completion_for_package(sbsp_socket_id);
}
/*
* EX: CPX-SP
* Ports Stack Stack(HOB) IioConfigIou
* ==========================================
* 0 CSTACK stack 0 IOU0
* 1A..1D PSTACKZ stack 1 IOU1
* 2A..2D PSTACK1 stack 2 IOU2
* 3A..3D PSTACK2 stack 4 IOU3
*/
int soc_get_stack_for_port(int port)
{
if (port == PORT_0)
return CSTACK;
else if (port >= PORT_1A && port <= PORT_1D)
return PSTACK0;
else if (port >= PORT_2A && port <= PORT_2D)
return PSTACK1;
else if (port >= PORT_3A && port <= PORT_3D)
return PSTACK2;
else
return -1;
}

View File

@ -142,48 +142,6 @@ static unsigned long acpi_fill_slit(unsigned long current)
return current;
}
/*
* EX: CPX-SP
* Ports Stack Stack(HOB) IioConfigIou
* ==========================================
* 0 CSTACK stack 0 IOU0
* 1A..1D PSTACKZ stack 1 IOU1
* 2A..2D PSTACK1 stack 2 IOU2
* 3A..3D PSTACK2 stack 4 IOU3
*/
static int get_stack_for_port(int port)
{
#if (CONFIG(SOC_INTEL_COOPERLAKE_SP))
if (port == PORT_0)
return CSTACK;
else if (port >= PORT_1A && port <= PORT_1D)
return PSTACK0;
else if (port >= PORT_2A && port <= PORT_2D)
return PSTACK1;
else if (port >= PORT_3A && port <= PORT_3D)
return PSTACK2;
else
return -1;
#endif /* SOC_INTEL_COOPERLAKE_SP */
#if (CONFIG(SOC_INTEL_SKYLAKE_SP))
if (port == PORT_0)
return CSTACK;
else if (port >= PORT_1A && port <= PORT_1D)
return PSTACK0;
else if (port >= PORT_2A && port <= PORT_2D)
return PSTACK1;
else if (port >= PORT_3A && port <= PORT_3D)
return PSTACK2;
else if (port >= PORT_4A && port <= PORT_4D)
return PSTACK3; // MCP0
else if (port >= PORT_5A && port <= PORT_5D)
return PSTACK4; // MCP1
else
return -1;
#endif /* SOC_INTEL_SKYLAKE_SP */
}
/*
* This function adds PCIe bridge device entry in DMAR table. If it is called
* in the context of ATSR subtable, it adds ATSR subtable when it is first called.
@ -193,7 +151,7 @@ static unsigned long acpi_create_dmar_ds_pci_br_for_port(unsigned long current,
bool is_atsr, bool *first)
{
if (get_stack_for_port(port) != stack)
if (soc_get_stack_for_port(port) != stack)
return 0;
const uint32_t bus = iio_resource.StackRes[stack].BusBase;

View File

@ -27,5 +27,6 @@ const struct SystemMemoryMapHob *get_system_memory_map(void);
void set_bios_init_completion(void);
unsigned int soc_get_num_cpus(void);
int soc_get_stack_for_port(int port);
#endif /* _SOC_UTIL_H_ */

View File

@ -394,4 +394,32 @@ void xeonsp_init_cpu_config(void)
}
}
/*
* EX: SKX-SP
* Ports Stack Stack(HOB) IioConfigIou
* ==========================================
* 0 CSTACK stack 0 IOU0
* 1A..1D PSTACKZ stack 1 IOU1
* 2A..2D PSTACK1 stack 2 IOU2
* 3A..3D PSTACK2 stack 3 IOU3
* 5A..4D PSTACK3 stack 4 IOU4
* 5A..5D PSTACK4 stack 5 IOU5
*/
int soc_get_stack_for_port(int port)
{
if (port == PORT_0)
return CSTACK;
else if (port >= PORT_1A && port <= PORT_1D)
return PSTACK0;
else if (port >= PORT_2A && port <= PORT_2D)
return PSTACK1;
else if (port >= PORT_3A && port <= PORT_3D)
return PSTACK2;
else if (port >= PORT_4A && port <= PORT_4D)
return PSTACK3; // MCP0
else if (port >= PORT_5A && port <= PORT_5D)
return PSTACK4; // MCP1
else
return -1;
}
#endif