Refactor code containing aux calls

Moved a lot of code from i915io.c to intel_dp.c with specific function calls

Change-Id: Ib2ed52b4f73ee0076e2dd68a26541e5bbe1366bc
Reviewed-on: https://gerrit.chromium.org/gerrit/63950
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/4429
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

src/drivers/intel/gma/i915.h

@@ -237,3 +237,30 @@ enum transcoder intel_ddi_get_transcoder(enum port port,
 
 void intel_dp_set_m_n_regs(struct intel_dp *intel_dp);
 void intel_dp_set_resolution(struct intel_dp *intel_dp);
+
+int intel_dp_i2c_write(struct intel_dp *intel_dp,
+		       u8 val);
+
+int intel_dp_i2c_read(struct intel_dp *intel_dp,
+		      u8 *val);
+
+int intel_dp_set_bw(struct intel_dp *intel_dp);
+int intel_dp_set_lane_count(struct intel_dp *intel_dp);
+int intel_dp_set_training_lane0(struct intel_dp *intel_dp,
+				u8 val);
+int intel_dp_set_training_pattern(struct intel_dp *intel_dp,
+				  u8 pat);
+
+int intel_dp_get_link_status(struct intel_dp *intel_dp,
+			     uint8_t link_status[DP_LINK_STATUS_SIZE]);
+
+int intel_dp_get_training_pattern(struct intel_dp *intel_dp,
+				  u8 *recv);
+
+int intel_dp_get_lane_count(struct intel_dp *intel_dp,
+			    u8 *recv);
+
+int intel_dp_get_lane_align_status(struct intel_dp *intel_dp,
+				   u8 *recv);
+
+

src/drivers/intel/gma/intel_dp.c

@@ -250,6 +250,40 @@ intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
 	return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
 }
 
+int intel_dp_set_bw(struct intel_dp *intel_dp)
+{
+	printk(BIOS_SPEW, "DP_LINK_BW_SET");
+	return intel_dp_aux_native_write_1(intel_dp,
+					   DP_LINK_BW_SET,
+					   intel_dp->link_bw);
+}
+
+int intel_dp_set_lane_count(struct intel_dp *intel_dp)
+{
+	printk(BIOS_SPEW, "DP_LANE_COUNT_SET");
+	return intel_dp_aux_native_write_1(intel_dp,
+					   DP_LANE_COUNT_SET,
+					   intel_dp->lane_count);
+}
+
+int intel_dp_set_training_pattern(struct intel_dp *intel_dp,
+				  u8 pat)
+{
+	printk(BIOS_SPEW, "DP_TRAINING_PATTERN_SET");
+	return intel_dp_aux_native_write_1(intel_dp,
+					   DP_TRAINING_PATTERN_SET,
+					   pat);
+}
+
+int intel_dp_set_training_lane0(struct intel_dp *intel_dp,
+				u8 val)
+{
+	printk(BIOS_SPEW, "DP_TRAINING_LANE0_SET");
+	return intel_dp_aux_native_write_1(intel_dp,
+					   DP_TRAINING_LANE0_SET,
+					   val);
+}
+
 /* read bytes from a native aux channel */
 static int
 intel_dp_aux_native_read(struct intel_dp *intel_dp,
@@ -381,6 +415,24 @@ intel_dp_i2c_aux_ch(struct intel_dp *intel_dp,
 	return -1;
 }
 
+int intel_dp_i2c_write(struct intel_dp *intel_dp,
+		       u8 val)
+{
+	return intel_dp_i2c_aux_ch(intel_dp,
+				   MODE_I2C_WRITE,
+				   val,
+				   NULL);
+}
+
+int intel_dp_i2c_read(struct intel_dp *intel_dp,
+		      u8 *val)
+{
+	return intel_dp_i2c_aux_ch(intel_dp,
+				   MODE_I2C_READ,
+				   0,
+				   val);
+}
+
 int
 intel_dp_i2c_init(struct intel_dp *intel_dp)
 {
@@ -990,7 +1042,7 @@ intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
  * Fetch AUX CH registers 0x202 - 0x207 which contain
  * link status information
  */
-static int
+int
 intel_dp_get_link_status(struct intel_dp *intel_dp,
 			 uint8_t link_status[DP_LINK_STATUS_SIZE])
 {
@@ -1728,7 +1780,7 @@ int
 intel_dp_get_max_downspread(struct intel_dp *intel_dp, u8 *max_downspread)
 {
 	int got, want = 1;
-	got = intel_dp_aux_native_read_retry(intel_dp, 0x000, max_downspread,
+	got = intel_dp_aux_native_read_retry(intel_dp, DP_MAX_DOWNSPREAD, max_downspread,
 					     want);
 	if (got < want) {
 		printk(BIOS_SPEW, "%s: got %d, wanted %d\n", __func__, got, want);
@@ -1761,3 +1813,30 @@ void intel_dp_set_resolution(struct intel_dp *intel_dp)
         io_i915_write32(intel_dp->vblank, VBLANK(intel_dp->transcoder));
         io_i915_write32(intel_dp->vsync,  VSYNC(intel_dp->transcoder));
 }
+
+int intel_dp_get_training_pattern(struct intel_dp *intel_dp,
+				  u8 *recv)
+{
+	return intel_dp_aux_native_read_retry(intel_dp,
+					      DP_TRAINING_PATTERN_SET,
+					      recv,
+					      0);
+}
+
+int intel_dp_get_lane_count(struct intel_dp *intel_dp,
+			    u8 *recv)
+{
+	return intel_dp_aux_native_read_retry(intel_dp,
+					      DP_LANE_COUNT_SET,
+					      recv,
+					      0);
+}
+
+int intel_dp_get_lane_align_status(struct intel_dp *intel_dp,
+				   u8 *recv)
+{
+	return intel_dp_aux_native_read_retry(intel_dp,
+					      DP_LANE_ALIGN_STATUS_UPDATED,
+					      recv,
+					      0);
+}

src/mainboard/google/slippy/gma.c

@@ -340,6 +340,31 @@ int intel_dp_bw_code_to_link_rate(u8 link_bw)
 	}
 }
 
+void mainboard_train_link(struct intel_dp *intel_dp);
+void mainboard_train_link(struct intel_dp *intel_dp)
+{
+	u8 read_val;
+	u8 link_status[DP_LINK_STATUS_SIZE];
+
+	io_i915_write32(0x80040000,DP_TP_CTL_A);
+	io_i915_write32( DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH |0x80000011,DP_A);
+
+	intel_dp_get_training_pattern(intel_dp, &read_val);
+	intel_dp_set_training_pattern(intel_dp, DP_TRAINING_PATTERN_1 | DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH);
+	intel_dp_get_lane_count(intel_dp, &read_val);
+	intel_dp_set_training_lane0(intel_dp, DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0);
+	intel_dp_get_link_status(intel_dp, link_status);
+
+	io_i915_write32(0x80040100,DP_TP_CTL_A);
+
+	intel_dp_get_training_pattern(intel_dp, &read_val);
+	intel_dp_set_training_pattern(intel_dp, DP_TRAINING_PATTERN_2 | DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH);
+	intel_dp_get_link_status(intel_dp, link_status);
+	intel_dp_get_lane_align_status(intel_dp, &read_val);
+	intel_dp_get_training_pattern(intel_dp, &read_val);
+	intel_dp_set_training_pattern(intel_dp, DP_TRAINING_PATTERN_DISABLE | DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH);
+}
+
 int i915lightup(unsigned int physbase, unsigned int iobase, unsigned int mmio,
 		unsigned int gfx);
 

src/mainboard/google/slippy/i915io.c

@@ -33,11 +33,15 @@ u32 auxout;
 u8 auxin[20];
 u8 msg[32];
 
+extern void mainboard_train_link(struct intel_dp *intel_dp);
+
 /* this function will either be renamed or subsumed into ./gma.c:i915_lightup */
 void runio(struct intel_dp *dp);
 
 void runio(struct intel_dp *dp)
 {
+	u8 read_val;
+
 	intel_dp_wait_panel_power_control(0xabcd0008);
 
 	/* vbios spins at this point. Some haswell weirdness? */
@@ -109,11 +113,8 @@ void runio(struct intel_dp *dp)
 
 	io_i915_write32(0x00000001,0x4f008);
 	io_i915_write32(0x00000012,0x4f014);
-	/* replace with a function: unsigned int intel_dp_get_max_downspread(dp); */
+
-	auxout = 1<<31 /* dp */|0x1<<28/*R*/|DP_MAX_DOWNSPREAD<<8|0x0|0x90000300;
+	intel_dp_get_max_downspread(dp, &read_val);
-printk(BIOS_SPEW, "DP_MAX_DOWNSPREAD");
-	unpack_aux(auxout, &msg[0], 4);
-	intel_dp_aux_ch(dp, msg, 4, auxin, 0);
 
 	intel_dp_set_m_n_regs(dp);
 
@@ -142,38 +143,12 @@ printk(BIOS_SPEW, "DP_MAX_DOWNSPREAD");
 	intel_dp_wait_panel_power_control(0xabcd000a);
 
 	/* what is this doing? Not sure yet. */
-	/* each block here needs to be a call to a function */
+	intel_dp_i2c_write(dp, 0x0);
-	auxout = 0<<31 /* i2c */|1<<30|0x0<<28/*W*/|0x50<<8|0x0|0x40005000;
+	intel_dp_i2c_read(dp, &read_val);
-	unpack_aux(auxout, &msg[0], 4);
+	intel_dp_i2c_write(dp, 0x04);
-	auxout = 0x00000000;
+	intel_dp_i2c_read(dp, &read_val);
-	unpack_aux(auxout, &msg[4], 4);
+	intel_dp_i2c_write(dp, 0x7e);
-	intel_dp_aux_ch(dp, msg, 5, auxin, 0);
+	intel_dp_i2c_read(dp, &read_val);
-
-	auxout = 0<<31 /* i2c */|0<<30|0x1<<28/*R*/|0x50<<8|0x3|0x10005003;
-	unpack_aux(auxout, &msg[0], 4);
-	intel_dp_aux_ch(dp, msg, 4, auxin, 3);
-
-	auxout = 0<<31 /* i2c */|1<<30|0x0<<28/*W*/|0x50<<8|0x0|0x40005000;
-	unpack_aux(auxout, &msg[0], 4);
-	auxout = 0x04000000;
-	unpack_aux(auxout, &msg[4], 4);
-	intel_dp_aux_ch(dp, msg, 5, auxin, 0);
-
-	auxout = 0<<31 /* i2c */|0<<30|0x1<<28/*R*/|0x50<<8|0x3|0x10005003;
-	unpack_aux(auxout, &msg[0], 4);
-	intel_dp_aux_ch(dp, msg, 4, auxin, 3);
-
-
-	auxout = 0<<31 /* i2c */|1<<30|0x0<<28/*W*/|0x50<<8|0x0|0x40005000;
-	unpack_aux(auxout, &msg[0], 4);
-	auxout = 0x7e000000;
-	unpack_aux(auxout, &msg[4], 4);
-	intel_dp_aux_ch(dp, msg, 5, auxin, 0);
-
-
-	auxout = 0<<31 /* i2c */|0<<30|0x1<<28/*R*/|0x50<<8|0x0|0x10005000;
-	unpack_aux(auxout, &msg[0], 4);
-	intel_dp_aux_ch(dp, msg, 4, auxin, 0);
 
 	/* this needs to be a call to a function */
 	io_i915_write32( DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SCRAMBLING_DISABLE_IRONLAKE | DP_SYNC_VS_HIGH |0x00000091,DP_A);
@@ -185,115 +160,10 @@ printk(BIOS_SPEW, "DP_MAX_DOWNSPREAD");
 	io_i915_write32( PANEL_PORT_SELECT_LVDS |(/* PANEL_POWER_UP_DELAY_MASK */0x1<<16)|(/* PANEL_LIGHT_ON_DELAY_MASK */0xa<<0)|0x0001000a,PCH_PP_ON_DELAYS);
 	io_i915_write32( PANEL_PORT_SELECT_LVDS |(/* PANEL_POWER_UP_DELAY_MASK */0x7d0<<16)|(/* PANEL_LIGHT_ON_DELAY_MASK */0xa<<0)|0x07d0000a,PCH_PP_ON_DELAYS);
 
+	intel_dp_set_bw(dp);
+	intel_dp_set_lane_count(dp);
 
-	/* create function: intel_dp_set_bw(dp, u8 bw); */
+	mainboard_train_link(dp);
-	auxout = 1<<31 /* dp */|0x0<<28/*W*/|DP_LINK_BW_SET<<8|0x0|0x80010000;
-	printk(BIOS_SPEW, "DP_LINK_BW_SET");
-	unpack_aux(auxout, &msg[0], 4);
-	auxout = 0x0a000480;
-	/*( DP_LINK_BW_2_7 &0xa)|0xffffffff8004000a*/
-	unpack_aux(auxout, &msg[4], 4);
-	intel_dp_aux_ch(dp, msg, 5, auxin, 0);
-
-	/* this info whould have been goten in intel_dp_get_dpcd. So that function should
-	 * set dp->lane_count but does not yet.
-	 */
-	auxout = 1<<31 /* dp */|0x1<<28/*R*/|DP_MAX_LANE_COUNT<<8|0x0|0x90000200;
-printk(BIOS_SPEW, "DP_MAX_LANE_COUNT");
-	unpack_aux(auxout, &msg[0], 4);
-	intel_dp_aux_ch(dp, msg, 4, auxin, 0);
-
-	/* create a function: intel_dp_set_lane_count(dp); gets lane count from dp->lane_count */
-	auxout = 1<<31 /* dp */|0x0<<28/*W*/|DP_LANE_COUNT_SET<<8|0x0|0x80010100;
-printk(BIOS_SPEW, "DP_LANE_COUNT_SET");
-	unpack_aux(auxout, &msg[0], 4);
-	auxout = 0x81000000;
-	/*0x00000081*/
-	unpack_aux(auxout, &msg[4], 4);
-	intel_dp_aux_ch(dp, msg, 5, auxin, 0);
-
-	io_i915_write32(0x80040000,DP_TP_CTL_A);
-	io_i915_write32( DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH |0x80000011,DP_A);
-
-	/* find or create: intel_dp_set_training_pattern(dp, pattern); */
-	auxout = 1<<31 /* dp */|0x1<<28/*R*/|DP_TRAINING_PATTERN_SET<<8|0x0|0x90010200;
-printk(BIOS_SPEW, "DP_TRAINING_PATTERN_SET");
-	unpack_aux(auxout, &msg[0], 4);
-	intel_dp_aux_ch(dp, msg, 4, auxin, 0);
-
-	/* why did they do it twice? */
-	auxout = 1<<31 /* dp */|0x0<<28/*W*/|DP_TRAINING_PATTERN_SET<<8|0x0|0x80010200;
-printk(BIOS_SPEW, "DP_TRAINING_PATTERN_SET");
-	unpack_aux(auxout, &msg[0], 4);
-	auxout = 0x01000000;
-	/* DP_TRAINING_PATTERN_1 | DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH |0x00000001*/
-	unpack_aux(auxout, &msg[4], 4);
-	intel_dp_aux_ch(dp, msg, 5, auxin, 0);
-
-	/* create a function */
-	auxout = 1<<31 /* dp */|0x1<<28/*R*/|DP_LANE_COUNT_SET<<8|0x0|0x90010100;
-printk(BIOS_SPEW, "DP_LANE_COUNT_SET");
-	unpack_aux(auxout, &msg[0], 4);
-	intel_dp_aux_ch(dp, msg, 4, auxin, 0);
-
-	/* create a function */
-	auxout = 1<<31 /* dp */|0x0<<28/*W*/|DP_TRAINING_LANE0_SET<<8|0x0|0x80010300;
-printk(BIOS_SPEW, "DP_TRAINING_LANE0_SET");
-	unpack_aux(auxout, &msg[0], 4);
-	auxout = 0x00000000;
-	/* DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0 |0x00000000*/
-	unpack_aux(auxout, &msg[4], 4);
-	intel_dp_aux_ch(dp, msg, 5, auxin, 0);
-
-	/* create a function */
-	auxout = 1<<31 /* dp */|0x1<<28/*R*/|DP_LANE0_1_STATUS<<8|0x1|0x90020201;
-printk(BIOS_SPEW, "DP_LANE0_1_STATUS");
-	unpack_aux(auxout, &msg[0], 4);
-	intel_dp_aux_ch(dp, msg, 4, auxin, 1);
-
-	io_i915_write32(0x80040100,DP_TP_CTL_A);
-
-	/* create a function */
-	auxout = 1<<31 /* dp */|0x1<<28/*R*/|DP_TRAINING_PATTERN_SET<<8|0x0|0x90010200;
-printk(BIOS_SPEW, "DP_TRAINING_PATTERN_SET");
-	unpack_aux(auxout, &msg[0], 4);
-	intel_dp_aux_ch(dp, msg, 4, auxin, 0);
-
-	/* create a function */
-	auxout = 1<<31 /* dp */|0x0<<28/*W*/|DP_TRAINING_PATTERN_SET<<8|0x0|0x80010200;
-printk(BIOS_SPEW, "DP_TRAINING_PATTERN_SET");
-	unpack_aux(auxout, &msg[0], 4);
-	auxout = 0x02000000;
-	/* DP_TRAINING_PATTERN_2 | DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH |0x00000002*/
-	unpack_aux(auxout, &msg[4], 4);
-	intel_dp_aux_ch(dp, msg, 5, auxin, 0);
-
-	/* create a function */
-	auxout = 1<<31 /* dp */|0x1<<28/*R*/|DP_LANE0_1_STATUS<<8|0x1|0x90020201;
-printk(BIOS_SPEW, "DP_LANE0_1_STATUS");
-	unpack_aux(auxout, &msg[0], 4);
-	intel_dp_aux_ch(dp, msg, 4, auxin, 1);
-
-	/* create a function */
-	auxout = 1<<31 /* dp */|0x1<<28/*R*/|DP_LANE_ALIGN_STATUS_UPDATED<<8|0x0|0x90020400;
-printk(BIOS_SPEW, "DP_LANE_ALIGN_STATUS_UPDATED");
-	unpack_aux(auxout, &msg[0], 4);
-	intel_dp_aux_ch(dp, msg, 4, auxin, 0);
-
-	/* create a function */
-	auxout = 1<<31 /* dp */|0x1<<28/*R*/|DP_TRAINING_PATTERN_SET<<8|0x0|0x90010200;
-printk(BIOS_SPEW, "DP_TRAINING_PATTERN_SET");
-	unpack_aux(auxout, &msg[0], 4);
-	intel_dp_aux_ch(dp, msg, 4, auxin, 0);
-
-	/* create a function */
-	auxout = 1<<31 /* dp */|0x0<<28/*W*/|DP_TRAINING_PATTERN_SET<<8|0x0|0x80010200;
-printk(BIOS_SPEW, "DP_TRAINING_PATTERN_SET");
-	unpack_aux(auxout, &msg[0], 4);
-	auxout = 0x00000000;
-	/* DP_TRAINING_PATTERN_DISABLE | DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH |0x00000000*/
-	unpack_aux(auxout, &msg[4], 4);
-	intel_dp_aux_ch(dp, msg, 5, auxin, 0);
 
 	/* need a function: intel_ddi_set_tp or similar */
 	io_i915_write32(0x80040200,DP_TP_CTL_A);
@@ -302,11 +172,9 @@ printk(BIOS_SPEW, "DP_TRAINING_PATTERN_SET");
 	io_i915_write32(0x03a903a9,BLC_PWM_PCH_CTL2);
 	io_i915_write32(0x80000000,BLC_PWM_PCH_CTL1);
 
-
 	io_i915_write32(0x00000400,0x4f044);
 	io_i915_write32(0x00000000,0x4f044);
 
-
 	/* some of this is not needed. */
 	io_i915_write32( PORTD_HOTPLUG_ENABLE | PORTB_HOTPLUG_ENABLE |0x10100010,SDEISR+0x30);
 	io_i915_write32( DIGITAL_PORTA_HOTPLUG_ENABLE |0x00000010,DIGITAL_PORT_HOTPLUG_CNTRL);