Refactor code containing aux calls
Moved a lot of code from i915io.c to intel_dp.c with specific function calls Change-Id: Ib2ed52b4f73ee0076e2dd68a26541e5bbe1366bc Reviewed-on: https://gerrit.chromium.org/gerrit/63950 Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/4429 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This commit is contained in:
Furquan Shaikh
Patrick Georgi
parent
771c3aca70
commit
997be3d2ee
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@ -237,3 +237,30 @@ enum transcoder intel_ddi_get_transcoder(enum port port,
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void intel_dp_set_m_n_regs(struct intel_dp *intel_dp);
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void intel_dp_set_resolution(struct intel_dp *intel_dp);
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int intel_dp_i2c_write(struct intel_dp *intel_dp,
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u8 val);
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int intel_dp_i2c_read(struct intel_dp *intel_dp,
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u8 *val);
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int intel_dp_set_bw(struct intel_dp *intel_dp);
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int intel_dp_set_lane_count(struct intel_dp *intel_dp);
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int intel_dp_set_training_lane0(struct intel_dp *intel_dp,
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u8 val);
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int intel_dp_set_training_pattern(struct intel_dp *intel_dp,
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u8 pat);
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int intel_dp_get_link_status(struct intel_dp *intel_dp,
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uint8_t link_status[DP_LINK_STATUS_SIZE]);
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int intel_dp_get_training_pattern(struct intel_dp *intel_dp,
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u8 *recv);
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int intel_dp_get_lane_count(struct intel_dp *intel_dp,
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u8 *recv);
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int intel_dp_get_lane_align_status(struct intel_dp *intel_dp,
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u8 *recv);
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@ -250,6 +250,40 @@ intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
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return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
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}
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int intel_dp_set_bw(struct intel_dp *intel_dp)
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{
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printk(BIOS_SPEW, "DP_LINK_BW_SET");
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return intel_dp_aux_native_write_1(intel_dp,
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DP_LINK_BW_SET,
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intel_dp->link_bw);
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}
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int intel_dp_set_lane_count(struct intel_dp *intel_dp)
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{
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printk(BIOS_SPEW, "DP_LANE_COUNT_SET");
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return intel_dp_aux_native_write_1(intel_dp,
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DP_LANE_COUNT_SET,
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intel_dp->lane_count);
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}
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int intel_dp_set_training_pattern(struct intel_dp *intel_dp,
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u8 pat)
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{
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printk(BIOS_SPEW, "DP_TRAINING_PATTERN_SET");
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return intel_dp_aux_native_write_1(intel_dp,
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DP_TRAINING_PATTERN_SET,
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pat);
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}
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int intel_dp_set_training_lane0(struct intel_dp *intel_dp,
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u8 val)
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{
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printk(BIOS_SPEW, "DP_TRAINING_LANE0_SET");
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return intel_dp_aux_native_write_1(intel_dp,
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DP_TRAINING_LANE0_SET,
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val);
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}
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/* read bytes from a native aux channel */
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static int
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intel_dp_aux_native_read(struct intel_dp *intel_dp,
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@ -381,6 +415,24 @@ intel_dp_i2c_aux_ch(struct intel_dp *intel_dp,
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return -1;
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}
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int intel_dp_i2c_write(struct intel_dp *intel_dp,
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u8 val)
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{
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return intel_dp_i2c_aux_ch(intel_dp,
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MODE_I2C_WRITE,
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val,
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NULL);
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}
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int intel_dp_i2c_read(struct intel_dp *intel_dp,
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u8 *val)
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{
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return intel_dp_i2c_aux_ch(intel_dp,
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MODE_I2C_READ,
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0,
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val);
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}
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int
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intel_dp_i2c_init(struct intel_dp *intel_dp)
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{
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@ -990,7 +1042,7 @@ intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
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* Fetch AUX CH registers 0x202 - 0x207 which contain
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* link status information
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*/
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static int
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int
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intel_dp_get_link_status(struct intel_dp *intel_dp,
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uint8_t link_status[DP_LINK_STATUS_SIZE])
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{
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@ -1728,7 +1780,7 @@ int
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intel_dp_get_max_downspread(struct intel_dp *intel_dp, u8 *max_downspread)
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{
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int got, want = 1;
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got = intel_dp_aux_native_read_retry(intel_dp, 0x000, max_downspread,
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got = intel_dp_aux_native_read_retry(intel_dp, DP_MAX_DOWNSPREAD, max_downspread,
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want);
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if (got < want) {
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printk(BIOS_SPEW, "%s: got %d, wanted %d\n", __func__, got, want);
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@ -1761,3 +1813,30 @@ void intel_dp_set_resolution(struct intel_dp *intel_dp)
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io_i915_write32(intel_dp->vblank, VBLANK(intel_dp->transcoder));
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io_i915_write32(intel_dp->vsync, VSYNC(intel_dp->transcoder));
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}
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int intel_dp_get_training_pattern(struct intel_dp *intel_dp,
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u8 *recv)
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{
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return intel_dp_aux_native_read_retry(intel_dp,
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DP_TRAINING_PATTERN_SET,
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recv,
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0);
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}
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int intel_dp_get_lane_count(struct intel_dp *intel_dp,
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u8 *recv)
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{
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return intel_dp_aux_native_read_retry(intel_dp,
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DP_LANE_COUNT_SET,
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recv,
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0);
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}
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int intel_dp_get_lane_align_status(struct intel_dp *intel_dp,
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u8 *recv)
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{
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return intel_dp_aux_native_read_retry(intel_dp,
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DP_LANE_ALIGN_STATUS_UPDATED,
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recv,
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0);
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}
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@ -340,6 +340,31 @@ int intel_dp_bw_code_to_link_rate(u8 link_bw)
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}
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}
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void mainboard_train_link(struct intel_dp *intel_dp);
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void mainboard_train_link(struct intel_dp *intel_dp)
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{
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u8 read_val;
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u8 link_status[DP_LINK_STATUS_SIZE];
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io_i915_write32(0x80040000,DP_TP_CTL_A);
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io_i915_write32( DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH |0x80000011,DP_A);
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intel_dp_get_training_pattern(intel_dp, &read_val);
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intel_dp_set_training_pattern(intel_dp, DP_TRAINING_PATTERN_1 | DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH);
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intel_dp_get_lane_count(intel_dp, &read_val);
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intel_dp_set_training_lane0(intel_dp, DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0);
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intel_dp_get_link_status(intel_dp, link_status);
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io_i915_write32(0x80040100,DP_TP_CTL_A);
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intel_dp_get_training_pattern(intel_dp, &read_val);
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intel_dp_set_training_pattern(intel_dp, DP_TRAINING_PATTERN_2 | DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH);
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intel_dp_get_link_status(intel_dp, link_status);
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intel_dp_get_lane_align_status(intel_dp, &read_val);
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intel_dp_get_training_pattern(intel_dp, &read_val);
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intel_dp_set_training_pattern(intel_dp, DP_TRAINING_PATTERN_DISABLE | DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH);
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}
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int i915lightup(unsigned int physbase, unsigned int iobase, unsigned int mmio,
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unsigned int gfx);
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@ -33,11 +33,15 @@ u32 auxout;
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u8 auxin[20];
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u8 msg[32];
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extern void mainboard_train_link(struct intel_dp *intel_dp);
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/* this function will either be renamed or subsumed into ./gma.c:i915_lightup */
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void runio(struct intel_dp *dp);
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void runio(struct intel_dp *dp)
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{
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u8 read_val;
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intel_dp_wait_panel_power_control(0xabcd0008);
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/* vbios spins at this point. Some haswell weirdness? */
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@ -109,11 +113,8 @@ void runio(struct intel_dp *dp)
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io_i915_write32(0x00000001,0x4f008);
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io_i915_write32(0x00000012,0x4f014);
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/* replace with a function: unsigned int intel_dp_get_max_downspread(dp); */
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auxout = 1<<31 /* dp */|0x1<<28/*R*/|DP_MAX_DOWNSPREAD<<8|0x0|0x90000300;
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printk(BIOS_SPEW, "DP_MAX_DOWNSPREAD");
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unpack_aux(auxout, &msg[0], 4);
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intel_dp_aux_ch(dp, msg, 4, auxin, 0);
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intel_dp_get_max_downspread(dp, &read_val);
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intel_dp_set_m_n_regs(dp);
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@ -142,38 +143,12 @@ printk(BIOS_SPEW, "DP_MAX_DOWNSPREAD");
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intel_dp_wait_panel_power_control(0xabcd000a);
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/* what is this doing? Not sure yet. */
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/* each block here needs to be a call to a function */
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auxout = 0<<31 /* i2c */|1<<30|0x0<<28/*W*/|0x50<<8|0x0|0x40005000;
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unpack_aux(auxout, &msg[0], 4);
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auxout = 0x00000000;
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unpack_aux(auxout, &msg[4], 4);
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intel_dp_aux_ch(dp, msg, 5, auxin, 0);
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auxout = 0<<31 /* i2c */|0<<30|0x1<<28/*R*/|0x50<<8|0x3|0x10005003;
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unpack_aux(auxout, &msg[0], 4);
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intel_dp_aux_ch(dp, msg, 4, auxin, 3);
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auxout = 0<<31 /* i2c */|1<<30|0x0<<28/*W*/|0x50<<8|0x0|0x40005000;
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unpack_aux(auxout, &msg[0], 4);
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auxout = 0x04000000;
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unpack_aux(auxout, &msg[4], 4);
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intel_dp_aux_ch(dp, msg, 5, auxin, 0);
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auxout = 0<<31 /* i2c */|0<<30|0x1<<28/*R*/|0x50<<8|0x3|0x10005003;
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unpack_aux(auxout, &msg[0], 4);
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intel_dp_aux_ch(dp, msg, 4, auxin, 3);
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auxout = 0<<31 /* i2c */|1<<30|0x0<<28/*W*/|0x50<<8|0x0|0x40005000;
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unpack_aux(auxout, &msg[0], 4);
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auxout = 0x7e000000;
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unpack_aux(auxout, &msg[4], 4);
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intel_dp_aux_ch(dp, msg, 5, auxin, 0);
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auxout = 0<<31 /* i2c */|0<<30|0x1<<28/*R*/|0x50<<8|0x0|0x10005000;
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unpack_aux(auxout, &msg[0], 4);
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intel_dp_aux_ch(dp, msg, 4, auxin, 0);
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intel_dp_i2c_write(dp, 0x0);
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intel_dp_i2c_read(dp, &read_val);
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intel_dp_i2c_write(dp, 0x04);
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intel_dp_i2c_read(dp, &read_val);
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intel_dp_i2c_write(dp, 0x7e);
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intel_dp_i2c_read(dp, &read_val);
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/* this needs to be a call to a function */
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io_i915_write32( DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SCRAMBLING_DISABLE_IRONLAKE | DP_SYNC_VS_HIGH |0x00000091,DP_A);
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@ -185,115 +160,10 @@ printk(BIOS_SPEW, "DP_MAX_DOWNSPREAD");
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io_i915_write32( PANEL_PORT_SELECT_LVDS |(/* PANEL_POWER_UP_DELAY_MASK */0x1<<16)|(/* PANEL_LIGHT_ON_DELAY_MASK */0xa<<0)|0x0001000a,PCH_PP_ON_DELAYS);
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io_i915_write32( PANEL_PORT_SELECT_LVDS |(/* PANEL_POWER_UP_DELAY_MASK */0x7d0<<16)|(/* PANEL_LIGHT_ON_DELAY_MASK */0xa<<0)|0x07d0000a,PCH_PP_ON_DELAYS);
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intel_dp_set_bw(dp);
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intel_dp_set_lane_count(dp);
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/* create function: intel_dp_set_bw(dp, u8 bw); */
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auxout = 1<<31 /* dp */|0x0<<28/*W*/|DP_LINK_BW_SET<<8|0x0|0x80010000;
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printk(BIOS_SPEW, "DP_LINK_BW_SET");
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unpack_aux(auxout, &msg[0], 4);
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auxout = 0x0a000480;
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/*( DP_LINK_BW_2_7 &0xa)|0xffffffff8004000a*/
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unpack_aux(auxout, &msg[4], 4);
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intel_dp_aux_ch(dp, msg, 5, auxin, 0);
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/* this info whould have been goten in intel_dp_get_dpcd. So that function should
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* set dp->lane_count but does not yet.
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*/
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auxout = 1<<31 /* dp */|0x1<<28/*R*/|DP_MAX_LANE_COUNT<<8|0x0|0x90000200;
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printk(BIOS_SPEW, "DP_MAX_LANE_COUNT");
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unpack_aux(auxout, &msg[0], 4);
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intel_dp_aux_ch(dp, msg, 4, auxin, 0);
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/* create a function: intel_dp_set_lane_count(dp); gets lane count from dp->lane_count */
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auxout = 1<<31 /* dp */|0x0<<28/*W*/|DP_LANE_COUNT_SET<<8|0x0|0x80010100;
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printk(BIOS_SPEW, "DP_LANE_COUNT_SET");
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unpack_aux(auxout, &msg[0], 4);
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auxout = 0x81000000;
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/*0x00000081*/
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unpack_aux(auxout, &msg[4], 4);
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intel_dp_aux_ch(dp, msg, 5, auxin, 0);
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io_i915_write32(0x80040000,DP_TP_CTL_A);
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io_i915_write32( DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH |0x80000011,DP_A);
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/* find or create: intel_dp_set_training_pattern(dp, pattern); */
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auxout = 1<<31 /* dp */|0x1<<28/*R*/|DP_TRAINING_PATTERN_SET<<8|0x0|0x90010200;
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printk(BIOS_SPEW, "DP_TRAINING_PATTERN_SET");
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unpack_aux(auxout, &msg[0], 4);
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intel_dp_aux_ch(dp, msg, 4, auxin, 0);
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/* why did they do it twice? */
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auxout = 1<<31 /* dp */|0x0<<28/*W*/|DP_TRAINING_PATTERN_SET<<8|0x0|0x80010200;
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printk(BIOS_SPEW, "DP_TRAINING_PATTERN_SET");
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unpack_aux(auxout, &msg[0], 4);
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auxout = 0x01000000;
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/* DP_TRAINING_PATTERN_1 | DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH |0x00000001*/
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unpack_aux(auxout, &msg[4], 4);
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intel_dp_aux_ch(dp, msg, 5, auxin, 0);
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/* create a function */
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auxout = 1<<31 /* dp */|0x1<<28/*R*/|DP_LANE_COUNT_SET<<8|0x0|0x90010100;
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printk(BIOS_SPEW, "DP_LANE_COUNT_SET");
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unpack_aux(auxout, &msg[0], 4);
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intel_dp_aux_ch(dp, msg, 4, auxin, 0);
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/* create a function */
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auxout = 1<<31 /* dp */|0x0<<28/*W*/|DP_TRAINING_LANE0_SET<<8|0x0|0x80010300;
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printk(BIOS_SPEW, "DP_TRAINING_LANE0_SET");
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unpack_aux(auxout, &msg[0], 4);
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auxout = 0x00000000;
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/* DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0 |0x00000000*/
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unpack_aux(auxout, &msg[4], 4);
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intel_dp_aux_ch(dp, msg, 5, auxin, 0);
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/* create a function */
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auxout = 1<<31 /* dp */|0x1<<28/*R*/|DP_LANE0_1_STATUS<<8|0x1|0x90020201;
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printk(BIOS_SPEW, "DP_LANE0_1_STATUS");
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unpack_aux(auxout, &msg[0], 4);
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intel_dp_aux_ch(dp, msg, 4, auxin, 1);
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io_i915_write32(0x80040100,DP_TP_CTL_A);
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/* create a function */
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auxout = 1<<31 /* dp */|0x1<<28/*R*/|DP_TRAINING_PATTERN_SET<<8|0x0|0x90010200;
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printk(BIOS_SPEW, "DP_TRAINING_PATTERN_SET");
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unpack_aux(auxout, &msg[0], 4);
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intel_dp_aux_ch(dp, msg, 4, auxin, 0);
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/* create a function */
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auxout = 1<<31 /* dp */|0x0<<28/*W*/|DP_TRAINING_PATTERN_SET<<8|0x0|0x80010200;
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printk(BIOS_SPEW, "DP_TRAINING_PATTERN_SET");
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unpack_aux(auxout, &msg[0], 4);
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auxout = 0x02000000;
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/* DP_TRAINING_PATTERN_2 | DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH |0x00000002*/
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unpack_aux(auxout, &msg[4], 4);
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intel_dp_aux_ch(dp, msg, 5, auxin, 0);
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/* create a function */
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auxout = 1<<31 /* dp */|0x1<<28/*R*/|DP_LANE0_1_STATUS<<8|0x1|0x90020201;
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printk(BIOS_SPEW, "DP_LANE0_1_STATUS");
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unpack_aux(auxout, &msg[0], 4);
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||||
intel_dp_aux_ch(dp, msg, 4, auxin, 1);
|
||||
|
||||
/* create a function */
|
||||
auxout = 1<<31 /* dp */|0x1<<28/*R*/|DP_LANE_ALIGN_STATUS_UPDATED<<8|0x0|0x90020400;
|
||||
printk(BIOS_SPEW, "DP_LANE_ALIGN_STATUS_UPDATED");
|
||||
unpack_aux(auxout, &msg[0], 4);
|
||||
intel_dp_aux_ch(dp, msg, 4, auxin, 0);
|
||||
|
||||
/* create a function */
|
||||
auxout = 1<<31 /* dp */|0x1<<28/*R*/|DP_TRAINING_PATTERN_SET<<8|0x0|0x90010200;
|
||||
printk(BIOS_SPEW, "DP_TRAINING_PATTERN_SET");
|
||||
unpack_aux(auxout, &msg[0], 4);
|
||||
intel_dp_aux_ch(dp, msg, 4, auxin, 0);
|
||||
|
||||
/* create a function */
|
||||
auxout = 1<<31 /* dp */|0x0<<28/*W*/|DP_TRAINING_PATTERN_SET<<8|0x0|0x80010200;
|
||||
printk(BIOS_SPEW, "DP_TRAINING_PATTERN_SET");
|
||||
unpack_aux(auxout, &msg[0], 4);
|
||||
auxout = 0x00000000;
|
||||
/* DP_TRAINING_PATTERN_DISABLE | DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH |0x00000000*/
|
||||
unpack_aux(auxout, &msg[4], 4);
|
||||
intel_dp_aux_ch(dp, msg, 5, auxin, 0);
|
||||
mainboard_train_link(dp);
|
||||
|
||||
/* need a function: intel_ddi_set_tp or similar */
|
||||
io_i915_write32(0x80040200,DP_TP_CTL_A);
|
||||
|
|
@ -302,11 +172,9 @@ printk(BIOS_SPEW, "DP_TRAINING_PATTERN_SET");
|
|||
io_i915_write32(0x03a903a9,BLC_PWM_PCH_CTL2);
|
||||
io_i915_write32(0x80000000,BLC_PWM_PCH_CTL1);
|
||||
|
||||
|
||||
io_i915_write32(0x00000400,0x4f044);
|
||||
io_i915_write32(0x00000000,0x4f044);
|
||||
|
||||
|
||||
/* some of this is not needed. */
|
||||
io_i915_write32( PORTD_HOTPLUG_ENABLE | PORTB_HOTPLUG_ENABLE |0x10100010,SDEISR+0x30);
|
||||
io_i915_write32( DIGITAL_PORTA_HOTPLUG_ENABLE |0x00000010,DIGITAL_PORT_HOTPLUG_CNTRL);
|
||||
|
|
|
|||
Loading…
Reference in New Issue