Update of the src/include/spd.h file with the following improvements:
* Added information on the relevant datasheet(s) and where to get them. * Added missing #defines for some other config bytes. * Documented all config bytes a bit better. * Renamed some #defines to hopefully make their names clearer. (closes #38) Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2506 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann
parent
3ab63e1401
commit
998a57c477
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@ -1,8 +1,8 @@
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/*
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* spd.h: Definitions for Serial Presence Detect (SPD) data
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* stored on SDRAM modules
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* This file is part of the LinuxBIOS project.
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*
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* Copyright (C) 2005 Digital Design Corporation
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* Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -16,66 +16,117 @@
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef __SPD_H_DEFINED
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#define __SPD_H_DEFINED
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/*
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* Serial Presence Detect (SPD) data stored on SDRAM modules.
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*
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* Datasheet:
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* - Name: PC SDRAM Serial Presence Detect (SPD) Specification
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* Revision 1.2A, December, 1997
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* - PDF: http://www.intel.com/design/chipsets/memory/spdsd12a.pdf
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*
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* Datasheet (alternative):
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* - Name: SERIAL PRESENCE DETECT STANDARD, General Standard
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* JEDEC Standard No. 21-C
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* - PDF: http://www.jedec.org/download/search/4_01_02_00R9.PDF
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*/
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// Byte numbers
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#define SPD_MEMORY_TYPE 2
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#define SPD_NUM_ROWS 3
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#define SPD_NUM_COLUMNS 4
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#define SPD_NUM_DIMM_BANKS 5
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#define SPD_MODULE_DATA_WIDTH_LSB 6
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#define SPD_MODULE_DATA_WIDTH_MSB 7
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#define SPD_MODULE_VOLTAGE 8
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#define SPD_MIN_CYCLE_TIME_AT_CAS_MAX 9
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#define SPD_DIMM_CONFIG_TYPE 11
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#define SPD_REFRESH 12
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#define SPD_PRIMARY_DRAM_WIDTH 13
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#define SPD_SUPPORTED_BURST_LENGTHS 16
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#define SPD_NUM_BANKS_PER_DRAM 17
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#define SPD_ACCEPTABLE_CAS_LATENCIES 18
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#define SPD_MODULE_ATTRIBUTES 21
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#define SPD_MIN_CYCLE_TIME_AT_CAS_REDUCED_05 23
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#define SPD_MIN_CYCLE_TIME_AT_CAS_REDUCED_10 25
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#define SPD_MIN_ROW_PRECHARGE_TIME 27
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#define SPD_MIN_RAS_TO_CAS_DELAY 29
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#define SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY 30
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#define SPD_ADDRESS_CMD_HOLD 33
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#ifndef _SPD_H_
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#define _SPD_H_
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/* Byte numbers. */
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#define SPD_NUM_MANUFACTURER_BYTES 0 /* Number of bytes used by module manufacturer */
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#define SPD_TOTAL_SPD_MEMORY_SIZE 1 /* Total SPD memory size */
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#define SPD_MEMORY_TYPE 2 /* (Fundamental) memory type */
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#define SPD_NUM_ROWS 3 /* Number of row address bits */
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#define SPD_NUM_COLUMNS 4 /* Number of column address bits */
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#define SPD_NUM_DIMM_BANKS 5 /* Number of module rows (banks) */
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#define SPD_MODULE_DATA_WIDTH_LSB 6 /* Module data width (LSB) */
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#define SPD_MODULE_DATA_WIDTH_MSB 7 /* Module data width (MSB) */
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#define SPD_MODULE_VOLTAGE 8 /* Module interface signal levels */
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#define SPD_MIN_CYCLE_TIME_AT_CAS_MAX 9 /* SDRAM cycle time (highest CAS latency), RAS access time (tRAC) */
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#define SPD_ACCESS_TIME_FROM_CLOCK 10 /* SDRAM access time from clock (highest CAS latency), CAS access time (Tac, tCAC) */
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#define SPD_DIMM_CONFIG_TYPE 11 /* Module configuration type */
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#define SPD_REFRESH 12 /* Refresh rate/type */
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#define SPD_PRIMARY_SDRAM_WIDTH 13 /* SDRAM width (primary SDRAM) */
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#define SPD_ERROR_CHECKING_SDRAM_WIDTH 14 /* Error checking SDRAM (data) width */
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#define SPD_MIN_CLOCK_DELAY_B2B_RAND_COLUMN 15 /* SDRAM device attributes, minimum clock delay for back to back random column */
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#define SPD_SUPPORTED_BURST_LENGTHS 16 /* SDRAM device attributes, burst lengths supported */
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#define SPD_NUM_BANKS_PER_SDRAM 17 /* SDRAM device attributes, number of banks on SDRAM device */
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#define SPD_ACCEPTABLE_CAS_LATENCIES 18 /* SDRAM device attributes, CAS latency */
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#define SPD_CS_LATENCY 19 /* SDRAM device attributes, CS latency */
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#define SPD_WE_LATENCY 20 /* SDRAM device attributes, WE latency */
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#define SPD_MODULE_ATTRIBUTES 21 /* SDRAM module attributes */
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#define SPD_DEVICE_ATTRIBUTES_GENERAL 22 /* SDRAM device attributes, general */
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#define SPD_SDRAM_CYCLE_TIME_2ND 23 /* SDRAM cycle time (2nd highest CAS latency) */
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#define SPD_ACCESS_TIME_FROM_CLOCK_2ND 24 /* SDRAM access from clock (2nd highest CAS latency) */
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#define SPD_SDRAM_CYCLE_TIME_3RD 25 /* SDRAM cycle time (3rd highest CAS latency) */
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#define SPD_ACCESS_TIME_FROM_CLOCK_3RD 26 /* SDRAM access from clock (3rd highest CAS latency) */
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#define SPD_MIN_ROW_PRECHARGE_TIME 27 /* Minimum row precharge time (Trp) */
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#define SPD_MIN_ROWACTIVE_TO_ROWACTIVE 28 /* Minimum row active to row active (Trrd) */
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#define SPD_MIN_RAS_TO_CAS_DELAY 29 /* Minimum RAS to CAS delay (Trcd) */
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#define SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY 30 /* Minimum RAS pulse width (Tras) */
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#define SPD_DENSITY_OF_EACH_ROW_ON_MODULE 31 /* Density of each row on module */
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#define SPD_CMD_SIGNAL_INPUT_SETUP_TIME 32 /* Command and address signal input setup time */
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#define SPD_CMD_SIGNAL_INPUT_HOLD_TIME 33 /* Command and address signal input hold time */
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#define SPD_DATA_SIGNAL_INPUT_SETUP_TIME 34 /* Data signal input setup time */
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#define SPD_DATA_SIGNAL_INPUT_HOLD_TIME 35 /* Data signal input hold time */
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#define SPD_SPD_DATA_REVISION_CODE 62 /* SPD data revision code */
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#define SPD_CHECKSUM_FOR_BYTES_0_TO_62 63 /* Checksum for bytes 0-62 */
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#define SPD_MANUFACTURER_JEDEC_ID_CODE 64 /* Manufacturer's JEDEC ID code, per EIA/JEP106 (bytes 64-71) */
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#define SPD_MANUFACTURING_LOCATION 72 /* Manufacturing location */
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#define SPD_MANUFACTURER_PART_NUMBER 73 /* Manufacturer's part number, in 6-bit ASCII (bytes 73-90) */
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#define SPD_REVISION_CODE 91 /* Revision code (bytes 91-92) */
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#define SPD_MANUFACTURING_DATE 93 /* Manufacturing date (byte 93: year, byte 94: week) */
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#define SPD_ASSEMBLY_SERIAL_NUMBER 95 /* Assembly serial number (bytes 95-98) */
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#define SPD_MANUFACTURER_SPECIFIC_DATA 99 /* Manufacturer specific data (bytes 99-125) */
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#define SPD_INTEL_SPEC_FOR_FREQUENCY 126 /* Intel specification for frequency */
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#define SPD_INTEL_SPEC_100_MHZ 127 /* Intel specification details for 100MHz support */
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// SPD_MEMORY_TYPE values
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#define MEMORY_TYPE_SDRAM_DDR 7
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/* SPD_MEMORY_TYPE values. */
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#define SPD_MEMORY_TYPE_FPM_DRAM 1
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#define SPD_MEMORY_TYPE_EDO 2
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#define SPD_MEMORY_TYPE_PIPELINED_NIBBLE 3
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#define SPD_MEMORY_TYPE_SDRAM 4
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#define SPD_MEMORY_TYPE_MULTIPLEXED_ROM 5
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#define SPD_MEMORY_TYPE_SGRAM_DDR 6
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#define SPD_MEMORY_TYPE_SDRAM_DDR 7
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#define SPD_MEMORY_TYPE_SDRAM_DDR2 8
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// SPD_MODULE_VOLTAGE values
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#define SPD_VOLTAGE_SSTL2 4
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/* SPD_MODULE_VOLTAGE values. */
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#define SPD_VOLTAGE_TTL 0 /* 5.0 Volt/TTL */
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#define SPD_VOLTAGE_LVTTL 1 /* LVTTL */
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#define SPD_VOLTAGE_HSTL 2 /* HSTL 1.5 */
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#define SPD_VOLTAGE_SSTL3 3 /* SSTL 3.3 */
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#define SPD_VOLTAGE_SSTL2 4 /* SSTL 2.5 */
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// SPD_DIMM_CONFIG_TYPE values
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#define ERROR_SCHEME_NONE 0
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#define ERROR_SCHEME_PARITY 1
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#define ERROR_SCHEME_ECC 2
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/* SPD_DIMM_CONFIG_TYPE values. */
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#define ERROR_SCHEME_NONE 0
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#define ERROR_SCHEME_PARITY 1
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#define ERROR_SCHEME_ECC 2
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// SPD_ACCEPTABLE_CAS_LATENCIES values
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#define SPD_CAS_LATENCY_1_0 0x01
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#define SPD_CAS_LATENCY_1_5 0x02
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#define SPD_CAS_LATENCY_2_0 0x04
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#define SPD_CAS_LATENCY_2_5 0x08
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#define SPD_CAS_LATENCY_3_0 0x10
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#define SPD_CAS_LATENCY_3_5 0x20
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#define SPD_CAS_LATENCY_4_0 0x40
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/* SPD_ACCEPTABLE_CAS_LATENCIES values. */
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// TODO: Check values.
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#define SPD_CAS_LATENCY_1_0 0x01
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#define SPD_CAS_LATENCY_1_5 0x02
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#define SPD_CAS_LATENCY_2_0 0x04
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#define SPD_CAS_LATENCY_2_5 0x08
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#define SPD_CAS_LATENCY_3_0 0x10
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#define SPD_CAS_LATENCY_3_5 0x20
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#define SPD_CAS_LATENCY_4_0 0x40
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// SPD_SUPPORTED_BURST_LENGTHS values
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#define SPD_BURST_LENGTH_1 1
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#define SPD_BURST_LENGTH_2 2
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#define SPD_BURST_LENGTH_4 4
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#define SPD_BURST_LENGTH_8 8
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#define SPD_BURST_LENGTH_PAGE (1<<7)
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/* SPD_SUPPORTED_BURST_LENGTHS values. */
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#define SPD_BURST_LENGTH_1 1
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#define SPD_BURST_LENGTH_2 2
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#define SPD_BURST_LENGTH_4 4
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#define SPD_BURST_LENGTH_8 8
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#define SPD_BURST_LENGTH_PAGE (1 << 7)
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/* SPD_MODULE_ATTRIBUTES values. */
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#define MODULE_BUFFERED 1
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#define MODULE_REGISTERED 2
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// SPD_MODULE_ATTRIBUTES values
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#define MODULE_BUFFERED 1
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#define MODULE_REGISTERED 2
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#endif /* _SPD_H_ */
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#endif // __SPD_H_DEFINED
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@ -93,8 +93,8 @@ static const uint8_t dual_channel_parameters[] = {
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SPD_NUM_COLUMNS,
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SPD_NUM_ROWS,
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SPD_NUM_DIMM_BANKS,
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SPD_PRIMARY_DRAM_WIDTH,
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SPD_NUM_BANKS_PER_DRAM
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SPD_PRIMARY_SDRAM_WIDTH,
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SPD_NUM_BANKS_PER_SDRAM
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};
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/*
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@ -560,7 +560,7 @@ static struct dimm_size sdram_spd_get_width(uint16_t dimm_socket_address)
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width.side1 = 0;
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width.side2 = 0;
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value = spd_read_byte(dimm_socket_address, SPD_PRIMARY_DRAM_WIDTH);
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value = spd_read_byte(dimm_socket_address, SPD_PRIMARY_SDRAM_WIDTH);
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die_on_spd_error(value);
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width.side1 = value & 0x7f; // Mask off bank 2 flag
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@ -625,7 +625,7 @@ static struct dimm_size spd_get_dimm_size(unsigned dimm_socket_address)
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sz.side2 += value; // Symmetric
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}
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value = spd_read_byte(dimm_socket_address, SPD_NUM_BANKS_PER_DRAM);
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value = spd_read_byte(dimm_socket_address, SPD_NUM_BANKS_PER_SDRAM);
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die_on_spd_error(value);
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value = log2(value);
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@ -701,7 +701,7 @@ static uint8_t spd_get_supported_dimms(const struct mem_controller *ctrl)
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if (channel0_dimm == 0)
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continue; // No such socket on this mainboard
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if (spd_read_byte(channel0_dimm, SPD_MEMORY_TYPE) != MEMORY_TYPE_SDRAM_DDR)
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if (spd_read_byte(channel0_dimm, SPD_MEMORY_TYPE) != SPD_MEMORY_TYPE_SDRAM_DDR)
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continue;
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#ifdef VALIDATE_DIMM_COMPATIBILITY
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@ -1325,7 +1325,7 @@ static void configure_e7501_cas_latency(const struct mem_controller *ctrl, uint8
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current_cas_latency >>= 1;
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if (current_cas_latency != 0) {
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value = spd_read_byte(dimm_socket_address, SPD_MIN_CYCLE_TIME_AT_CAS_REDUCED_05);
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value = spd_read_byte(dimm_socket_address, SPD_SDRAM_CYCLE_TIME_2ND);
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if(value < 0 ) goto hw_err;
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if(value > 0x75)
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dimm_compatible_cas_latencies &= ~current_cas_latency;
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@ -1334,7 +1334,7 @@ static void configure_e7501_cas_latency(const struct mem_controller *ctrl, uint8
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// Can we support the next-highest CAS# latency (max - 1.0)?
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current_cas_latency >>= 1;
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if (current_cas_latency != 0) {
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value = spd_read_byte(dimm_socket_address, SPD_MIN_CYCLE_TIME_AT_CAS_REDUCED_10);
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value = spd_read_byte(dimm_socket_address, SPD_SDRAM_CYCLE_TIME_3RD);
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if(value < 0 ) goto hw_err;
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if(value > 0x75)
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dimm_compatible_cas_latencies &= ~current_cas_latency;
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@ -1489,11 +1489,11 @@ static void configure_e7501_dram_controller_mode(const struct mem_controller *ct
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#ifdef SUSPICIOUS_LOOKING_CODE
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// SJM NOTE: This code doesn't look right. SPD values are an order of magnitude smaller
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// than the clock period of the memory controller. Also, no other northbridge
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// looks at SPD_ADDRESS_CMD_HOLD.
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// looks at SPD_CMD_SIGNAL_INPUT_HOLD_TIME.
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// Switch to 2 clocks for address/command if required by any one of the DIMMs
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// NOTE: At 133 MHz, 1 clock == 7.52 ns
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value = spd_read_byte(dimm_socket_address, SPD_ADDRESS_CMD_HOLD);
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value = spd_read_byte(dimm_socket_address, SPD_CMD_SIGNAL_INPUT_HOLD_TIME);
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die_on_spd_error(value);
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if(value >= 0xa0) { /* At 133MHz this constant should be 0x75 */
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controller_mode &= ~(1<<16); /* Use two clock cyles instead of one */
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