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soc/intel/common/cache_as_ram.S: Add macro to clear CAR 

Add a macro to clear CAR which is replicated 3 times in this code.

TEST: with BUILD_TIMELESS=1 the resulting binary is identical.

Change-Id: Iec28e3f393c4fe222bfb0d5358f815691ec199ae
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Arthur Heymans 2019-11-25 09:56:20 +01:00 committed by Patrick Georgi
parent 64c9c6d54c
commit 99a48bc824
1 changed files with 22 additions and 20 deletions
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42
src/soc/intel/common/block/cpu/car/cache_as_ram.S
View File

@ -41,6 +41,23 @@
decl %ecx
.endm
/*
* macro: clear_car
* Clears the region between CONFIG_DCACHE_RAM_BASE and
* CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE to populate
* cachelines.
* Clobbers %eax, %ecx, %edi.
*/
.macro clear_car
/* Clear the cache memory region. This will also fill up the cache */
movl $CONFIG_DCACHE_RAM_BASE, %edi
movl $CONFIG_DCACHE_RAM_SIZE, %ecx
shr $0x02, %ecx
xor %eax, %eax
cld
rep stosl
.endm
.global bootblock_pre_c_entry
bootblock_pre_c_entry:
@ -256,13 +273,7 @@ car_nem:
post_code(0x26)
/* Clear the cache memory region. This will also fill up the cache */
movl $CONFIG_DCACHE_RAM_BASE, %edi
movl $CONFIG_DCACHE_RAM_SIZE, %ecx
shr $0x02, %ecx
xor %eax, %eax
cld
rep stosl
clear_car
post_code(0x27)
@ -353,13 +364,7 @@ car_cqos:
post_code(0x26)
/* Clear the cache memory region. This will also fill up the cache */
movl $CONFIG_DCACHE_RAM_BASE, %edi
movl $CONFIG_DCACHE_RAM_SIZE, %ecx
shr $0x02, %ecx
xor %eax, %eax
cld
rep stosl
clear_car
post_code(0x27)
@ -518,12 +523,9 @@ set_eviction_mask:
movl $0x02, %eax
#endif
wrmsr
movl $CONFIG_DCACHE_RAM_BASE, %edi
movl $CONFIG_DCACHE_RAM_SIZE, %ecx
shr $0x02, %ecx
xor %eax, %eax
cld
rep stosl
clear_car
/*
* Set IA32_PQR_ASSOC
* At this stage we apply LLC_WAY_MASK_1 to the cache.