soc/intel/common/cache_as_ram.S: Add macro to clear CAR
Add a macro to clear CAR which is replicated 3 times in this code. TEST: with BUILD_TIMELESS=1 the resulting binary is identical. Change-Id: Iec28e3f393c4fe222bfb0d5358f815691ec199ae Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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@ -41,6 +41,23 @@
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decl %ecx
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decl %ecx
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.endm
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.endm
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/*
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* macro: clear_car
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* Clears the region between CONFIG_DCACHE_RAM_BASE and
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* CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE to populate
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* cachelines.
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* Clobbers %eax, %ecx, %edi.
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*/
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.macro clear_car
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/* Clear the cache memory region. This will also fill up the cache */
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movl $CONFIG_DCACHE_RAM_BASE, %edi
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movl $CONFIG_DCACHE_RAM_SIZE, %ecx
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shr $0x02, %ecx
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xor %eax, %eax
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cld
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rep stosl
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.endm
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.global bootblock_pre_c_entry
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.global bootblock_pre_c_entry
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bootblock_pre_c_entry:
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bootblock_pre_c_entry:
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@ -256,13 +273,7 @@ car_nem:
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post_code(0x26)
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post_code(0x26)
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/* Clear the cache memory region. This will also fill up the cache */
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clear_car
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movl $CONFIG_DCACHE_RAM_BASE, %edi
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movl $CONFIG_DCACHE_RAM_SIZE, %ecx
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shr $0x02, %ecx
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xor %eax, %eax
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cld
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rep stosl
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post_code(0x27)
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post_code(0x27)
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@ -353,13 +364,7 @@ car_cqos:
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post_code(0x26)
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post_code(0x26)
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/* Clear the cache memory region. This will also fill up the cache */
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clear_car
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movl $CONFIG_DCACHE_RAM_BASE, %edi
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movl $CONFIG_DCACHE_RAM_SIZE, %ecx
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shr $0x02, %ecx
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xor %eax, %eax
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cld
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rep stosl
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post_code(0x27)
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post_code(0x27)
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@ -518,12 +523,9 @@ set_eviction_mask:
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movl $0x02, %eax
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movl $0x02, %eax
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#endif
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#endif
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wrmsr
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wrmsr
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movl $CONFIG_DCACHE_RAM_BASE, %edi
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movl $CONFIG_DCACHE_RAM_SIZE, %ecx
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clear_car
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shr $0x02, %ecx
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xor %eax, %eax
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cld
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rep stosl
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/*
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/*
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* Set IA32_PQR_ASSOC
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* Set IA32_PQR_ASSOC
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* At this stage we apply LLC_WAY_MASK_1 to the cache.
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* At this stage we apply LLC_WAY_MASK_1 to the cache.
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