mainboard/msi/ms9185/romstage: Use tabs for indents
Change-Id: I101462105da31654032ac7e6abd3f9423ad7a7ef Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16736 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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@ -50,14 +50,14 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl)
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{
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#define SMBUS_SWITCH1 0x70
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#define SMBUS_SWITCH2 0x72
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unsigned device = (ctrl->channel0[0]) >> 8;
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smbus_send_byte(SMBUS_SWITCH1, device & 0x0f);
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smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f );
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unsigned device = (ctrl->channel0[0]) >> 8;
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smbus_send_byte(SMBUS_SWITCH1, device & 0x0f);
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smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f );
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}
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static inline int spd_read_byte(unsigned device, unsigned address)
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{
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return smbus_read_byte(device, address);
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return smbus_read_byte(device, address);
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}
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#include <northbridge/amd/amdk8/f.h>
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@ -77,131 +77,131 @@ static inline int spd_read_byte(unsigned device, unsigned address)
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void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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{
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static const uint16_t spd_addr[] = {
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//first node
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RC0|DIMM0, RC0|DIMM2, RC0|DIMM4, RC0|DIMM6,
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RC0|DIMM1, RC0|DIMM3, RC0|DIMM5, RC0|DIMM7,
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//second node
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RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6,
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RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7,
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};
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static const uint16_t spd_addr[] = {
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//first node
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RC0|DIMM0, RC0|DIMM2, RC0|DIMM4, RC0|DIMM6,
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RC0|DIMM1, RC0|DIMM3, RC0|DIMM5, RC0|DIMM7,
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//second node
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RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6,
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RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7,
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};
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struct sys_info *sysinfo = &sysinfo_car;
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int needs_reset;
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unsigned bsp_apicid = 0;
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int needs_reset;
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unsigned bsp_apicid = 0;
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if (!cpu_init_detectedx && boot_cpu()) {
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if (!cpu_init_detectedx && boot_cpu()) {
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/* Nothing special needs to be done to find bus 0 */
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/* Allow the HT devices to be found */
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enumerate_ht_chain();
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bcm5785_enable_lpc();
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//enable RTC
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pc87417_enable_dev(RTC_DEV);
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}
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}
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if (bist == 0)
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bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
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if (bist == 0)
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bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
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pc87417_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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console_init();
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pc87417_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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console_init();
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// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
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/* Halt if there was a built in self test failure */
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report_bist_failure(bist);
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/* Halt if there was a built in self test failure */
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report_bist_failure(bist);
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printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
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printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
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setup_ms9185_resource_map();
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setup_ms9185_resource_map();
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#if 0
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dump_pci_device(PCI_DEV(0, 0x18, 0));
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dump_pci_device(PCI_DEV(0, 0x19, 0));
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dump_pci_device(PCI_DEV(0, 0x18, 0));
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dump_pci_device(PCI_DEV(0, 0x19, 0));
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#endif
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printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
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printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
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setup_coherent_ht_domain();
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setup_coherent_ht_domain();
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wait_all_core0_started();
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wait_all_core0_started();
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#if CONFIG_LOGICAL_CPUS
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// It is said that we should start core1 after all core0 launched
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/* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
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* So here need to make sure last core0 is started, esp for two way system,
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* (there may be apic id conflicts in that case)
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*/
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start_other_cores();
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// It is said that we should start core1 after all core0 launched
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/* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
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* So here need to make sure last core0 is started, esp for two way system,
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* (there may be apic id conflicts in that case)
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*/
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start_other_cores();
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//bx_a010- wait_all_other_cores_started(bsp_apicid);
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#endif
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/* it will set up chains and store link pair for optimization later */
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ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
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/* it will set up chains and store link pair for optimization later */
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ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
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bcm5785_early_setup();
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bcm5785_early_setup();
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#if 0
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//it your CPU min fid is 1G, you can change HT to 1G and FID to max one time.
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needs_reset = optimize_link_coherent_ht();
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needs_reset |= optimize_link_incoherent_ht(sysinfo);
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//it your CPU min fid is 1G, you can change HT to 1G and FID to max one time.
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needs_reset = optimize_link_coherent_ht();
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needs_reset |= optimize_link_incoherent_ht(sysinfo);
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#endif
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#if CONFIG_SET_FIDVID
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{
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msr_t msr;
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msr = rdmsr(0xc0010042);
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printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
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}
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enable_fid_change();
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enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
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init_fidvid_bsp(bsp_apicid);
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// show final fid and vid
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{
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msr_t msr;
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msr = rdmsr(0xc0010042);
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printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo);
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}
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{
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msr_t msr;
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msr = rdmsr(0xc0010042);
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printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
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}
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enable_fid_change();
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enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
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init_fidvid_bsp(bsp_apicid);
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// show final fid and vid
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{
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msr_t msr;
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msr = rdmsr(0xc0010042);
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printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo);
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}
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#endif
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#if 1
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needs_reset = optimize_link_coherent_ht();
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needs_reset |= optimize_link_incoherent_ht(sysinfo);
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needs_reset = optimize_link_coherent_ht();
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needs_reset |= optimize_link_incoherent_ht(sysinfo);
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// fidvid change will issue one LDTSTOP and the HT change will be effective too
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if (needs_reset) {
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printk(BIOS_INFO, "ht reset -\n");
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soft_reset();
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}
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// fidvid change will issue one LDTSTOP and the HT change will be effective too
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if (needs_reset) {
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printk(BIOS_INFO, "ht reset -\n");
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soft_reset();
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}
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#endif
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allow_all_aps_stop(bsp_apicid);
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allow_all_aps_stop(bsp_apicid);
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//It's the time to set ctrl in sysinfo now;
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fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
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//It's the time to set ctrl in sysinfo now;
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fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
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enable_smbus();
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enable_smbus();
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#if 0
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int i;
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for(i = 0; i < 2; i++) {
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activate_spd_rom(sysinfo->ctrl+i);
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dump_smbus_registers();
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}
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int i;
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for(i = 0; i < 2; i++) {
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activate_spd_rom(sysinfo->ctrl+i);
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dump_smbus_registers();
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}
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#endif
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//do we need apci timer, tsc...., only debug need it for better output
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/* all ap stopped? */
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//do we need apci timer, tsc...., only debug need it for better output
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/* all ap stopped? */
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// init_timer(); // Need to use TMICT to synchronize FID/VID
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sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
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sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
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#if 0
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print_pci_devices();
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print_pci_devices();
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#endif
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#if 0
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// dump_pci_devices();
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dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98);
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dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98);
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dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98);
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dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98);
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#endif
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post_cache_as_ram();
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post_cache_as_ram();
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}
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