GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mainboard/msi/ms9185/romstage: Use tabs for indents 

Change-Id: I101462105da31654032ac7e6abd3f9423ad7a7ef
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16736
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Elyes HAOUAS 2016-09-25 15:21:37 +02:00 committed by Patrick Georgi
parent 02fdb3e014
commit 99a92ac722
1 changed files with 78 additions and 78 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

156
src/mainboard/msi/ms9185/romstage.c
View File

@ -50,14 +50,14 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl)
{ {
#define SMBUS_SWITCH1 0x70 #define SMBUS_SWITCH1 0x70
#define SMBUS_SWITCH2 0x72 #define SMBUS_SWITCH2 0x72
unsigned device = (ctrl->channel0[0]) >> 8; unsigned device = (ctrl->channel0[0]) >> 8;
smbus_send_byte(SMBUS_SWITCH1, device & 0x0f); smbus_send_byte(SMBUS_SWITCH1, device & 0x0f);
smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f ); smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f );
} }
static inline int spd_read_byte(unsigned device, unsigned address) static inline int spd_read_byte(unsigned device, unsigned address)
{ {
return smbus_read_byte(device, address); return smbus_read_byte(device, address);
} }
#include <northbridge/amd/amdk8/f.h> #include <northbridge/amd/amdk8/f.h>
@ -77,131 +77,131 @@ static inline int spd_read_byte(unsigned device, unsigned address)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
static const uint16_t spd_addr[] = { static const uint16_t spd_addr[] = {
//first node //first node
RC0|DIMM0, RC0|DIMM2, RC0|DIMM4, RC0|DIMM6, RC0|DIMM0, RC0|DIMM2, RC0|DIMM4, RC0|DIMM6,
RC0|DIMM1, RC0|DIMM3, RC0|DIMM5, RC0|DIMM7, RC0|DIMM1, RC0|DIMM3, RC0|DIMM5, RC0|DIMM7,
//second node //second node
RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6, RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6,
RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7, RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7,
}; };
struct sys_info *sysinfo = &sysinfo_car; struct sys_info *sysinfo = &sysinfo_car;
int needs_reset; int needs_reset;
unsigned bsp_apicid = 0; unsigned bsp_apicid = 0;
if (!cpu_init_detectedx && boot_cpu()) { if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */ /* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */ /* Allow the HT devices to be found */
enumerate_ht_chain(); enumerate_ht_chain();
bcm5785_enable_lpc(); bcm5785_enable_lpc();
//enable RTC //enable RTC
pc87417_enable_dev(RTC_DEV); pc87417_enable_dev(RTC_DEV);
} }
if (bist == 0) if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
pc87417_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); pc87417_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init(); console_init();
// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
/* Halt if there was a built in self test failure */ /* Halt if there was a built in self test failure */
report_bist_failure(bist); report_bist_failure(bist);
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
setup_ms9185_resource_map(); setup_ms9185_resource_map();
#if 0 #if 0
dump_pci_device(PCI_DEV(0, 0x18, 0)); dump_pci_device(PCI_DEV(0, 0x18, 0));
dump_pci_device(PCI_DEV(0, 0x19, 0)); dump_pci_device(PCI_DEV(0, 0x19, 0));
#endif #endif
printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid); printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
setup_coherent_ht_domain(); setup_coherent_ht_domain();
wait_all_core0_started(); wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS #if CONFIG_LOGICAL_CPUS
// It is said that we should start core1 after all core0 launched // It is said that we should start core1 after all core0 launched
/* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
* So here need to make sure last core0 is started, esp for two way system, * So here need to make sure last core0 is started, esp for two way system,
* (there may be apic id conflicts in that case) * (there may be apic id conflicts in that case)
*/ */
start_other_cores(); start_other_cores();
//bx_a010- wait_all_other_cores_started(bsp_apicid); //bx_a010- wait_all_other_cores_started(bsp_apicid);
#endif #endif
/* it will set up chains and store link pair for optimization later */ /* it will set up chains and store link pair for optimization later */
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
bcm5785_early_setup(); bcm5785_early_setup();
#if 0 #if 0
//it your CPU min fid is 1G, you can change HT to 1G and FID to max one time. //it your CPU min fid is 1G, you can change HT to 1G and FID to max one time.
needs_reset = optimize_link_coherent_ht(); needs_reset = optimize_link_coherent_ht();
needs_reset |= optimize_link_incoherent_ht(sysinfo); needs_reset |= optimize_link_incoherent_ht(sysinfo);
#endif #endif
#if CONFIG_SET_FIDVID #if CONFIG_SET_FIDVID
{ {
msr_t msr; msr_t msr;
msr = rdmsr(0xc0010042); msr = rdmsr(0xc0010042);
printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo); printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
} }
enable_fid_change(); enable_fid_change();
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
init_fidvid_bsp(bsp_apicid); init_fidvid_bsp(bsp_apicid);
// show final fid and vid // show final fid and vid
{ {
msr_t msr; msr_t msr;
msr = rdmsr(0xc0010042); msr = rdmsr(0xc0010042);
printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo); printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo);
} }
#endif #endif
#if 1 #if 1
needs_reset = optimize_link_coherent_ht(); needs_reset = optimize_link_coherent_ht();
needs_reset |= optimize_link_incoherent_ht(sysinfo); needs_reset |= optimize_link_incoherent_ht(sysinfo);
// fidvid change will issue one LDTSTOP and the HT change will be effective too // fidvid change will issue one LDTSTOP and the HT change will be effective too
if (needs_reset) { if (needs_reset) {
printk(BIOS_INFO, "ht reset -\n"); printk(BIOS_INFO, "ht reset -\n");
soft_reset(); soft_reset();
} }
#endif #endif
allow_all_aps_stop(bsp_apicid); allow_all_aps_stop(bsp_apicid);
//It's the time to set ctrl in sysinfo now; //It's the time to set ctrl in sysinfo now;
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
enable_smbus(); enable_smbus();
#if 0 #if 0
int i; int i;
for(i = 0; i < 2; i++) { for(i = 0; i < 2; i++) {
activate_spd_rom(sysinfo->ctrl+i); activate_spd_rom(sysinfo->ctrl+i);
dump_smbus_registers(); dump_smbus_registers();
} }
#endif #endif
//do we need apci timer, tsc...., only debug need it for better output //do we need apci timer, tsc...., only debug need it for better output
/* all ap stopped? */ /* all ap stopped? */
// init_timer(); // Need to use TMICT to synchronize FID/VID // init_timer(); // Need to use TMICT to synchronize FID/VID
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
#if 0 #if 0
print_pci_devices(); print_pci_devices();
#endif #endif
#if 0 #if 0
// dump_pci_devices(); // dump_pci_devices();
dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98); dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98);
dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98); dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98);
#endif #endif
post_cache_as_ram(); post_cache_as_ram();
} }