diff --git a/src/mainboard/asrock/e350m1/BiosCallOuts.c b/src/mainboard/asrock/e350m1/BiosCallOuts.c
index de5d547ec2..ae67c3fd6e 100644
--- a/src/mainboard/asrock/e350m1/BiosCallOuts.c
+++ b/src/mainboard/asrock/e350m1/BiosCallOuts.c
@@ -377,7 +377,7 @@ AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 {
   AGESA_STATUS        Status;
 
-  Status = agesawrapper_amdlaterunaptask (Data, ConfigPtr);
+  Status = agesawrapper_amdlaterunaptask (Func, Data, ConfigPtr);
   return Status;
 }
 
diff --git a/src/mainboard/asrock/e350m1/agesawrapper.c b/src/mainboard/asrock/e350m1/agesawrapper.c
index e98d874b4b..802e00e1fe 100644
--- a/src/mainboard/asrock/e350m1/agesawrapper.c
+++ b/src/mainboard/asrock/e350m1/agesawrapper.c
@@ -435,42 +435,6 @@ UINT32
 agesawrapper_amdinitlate (
   VOID
   )
-{
-  AGESA_STATUS Status;
-  AMD_INTERFACE_PARAMS AmdParamStruct = {0};
-  AMD_LATE_PARAMS *AmdLateParams;
-
-  return 0; // this causes bad ACPI SSDT, need to debug
-
-  AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE;
-  AmdParamStruct.AllocationMethod = PostMemDram;
-  AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
-  AmdCreateStruct (&AmdParamStruct);
-  AmdLateParams = (AMD_LATE_PARAMS *)AmdParamStruct.NewStructPtr;
-  Status = AmdInitLate (AmdLateParams);
-  if (Status != AGESA_SUCCESS) {
-    agesawrapper_amdreadeventlog();
-    ASSERT(Status == AGESA_SUCCESS);
-  }
-
-  DmiTable    = AmdLateParams->DmiTable;
-  AcpiPstate  = AmdLateParams->AcpiPState;
-  AcpiSrat    = AmdLateParams->AcpiSrat;
-  AcpiSlit    = AmdLateParams->AcpiSlit;
-
-  AcpiWheaMce = AmdLateParams->AcpiWheaMce;
-  AcpiWheaCmc = AmdLateParams->AcpiWheaCmc;
-  AcpiAlib    = AmdLateParams->AcpiAlib;
-
-  AmdReleaseStruct (&AmdParamStruct);
-  return (UINT32)Status;
-}
-
-UINT32 
-agesawrapper_amdlaterunaptask (
-  UINT32 Data, 
-  VOID *ConfigPtr
-  )
 {
   AGESA_STATUS Status;
   AMD_LATE_PARAMS AmdLateParams;
@@ -485,20 +449,52 @@ agesawrapper_amdlaterunaptask (
   AmdLateParams.StdHeader.Func = 0;
   AmdLateParams.StdHeader.ImageBasePtr = 0;
 
-  Status = AmdLateRunApTask (&AmdLateParams);
+  Status = AmdInitLate (&AmdLateParams);
   if (Status != AGESA_SUCCESS) {
     agesawrapper_amdreadeventlog();
     ASSERT(Status == AGESA_SUCCESS);
   }
 
-  DmiTable       = AmdLateParams.DmiTable;
-  AcpiPstate     = AmdLateParams.AcpiPState;
-  AcpiSrat       = AmdLateParams.AcpiSrat;
-  AcpiSlit       = AmdLateParams.AcpiSlit;
+  DmiTable    = AmdLateParams.DmiTable;
+  AcpiPstate  = AmdLateParams.AcpiPState;
+  AcpiSrat    = AmdLateParams.AcpiSrat;
+  AcpiSlit    = AmdLateParams.AcpiSlit;
 
-  AcpiWheaMce    = AmdLateParams.AcpiWheaMce;
-  AcpiWheaCmc    = AmdLateParams.AcpiWheaCmc;
-  AcpiAlib       = AmdLateParams.AcpiAlib;
+  AcpiWheaMce = AmdLateParams.AcpiWheaMce;
+  AcpiWheaCmc = AmdLateParams.AcpiWheaCmc;
+  AcpiAlib    = AmdLateParams.AcpiAlib;
+
+  return (UINT32)Status;
+}
+
+UINT32 
+agesawrapper_amdlaterunaptask (
+  UINT32 Func, 
+  UINT32 Data, 
+  VOID *ConfigPtr
+  )
+{
+  AGESA_STATUS Status;
+  AP_EXE_PARAMS ApExeParams;
+
+  LibAmdMemFill (&ApExeParams,
+                 0,
+                 sizeof (AP_EXE_PARAMS),
+                 &(ApExeParams.StdHeader));
+
+  ApExeParams.StdHeader.AltImageBasePtr = 0;
+  ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+  ApExeParams.StdHeader.Func = 0;
+  ApExeParams.StdHeader.ImageBasePtr = 0;
+  ApExeParams.StdHeader.ImageBasePtr = 0;
+  ApExeParams.FunctionNumber = Func;
+  ApExeParams.RelatedDataBlock = ConfigPtr;
+
+  Status = AmdLateRunApTask (&ApExeParams);
+  if (Status != AGESA_SUCCESS) {
+    agesawrapper_amdreadeventlog();
+    ASSERT(Status == AGESA_SUCCESS);
+  }
 
   return (UINT32)Status;
 }
diff --git a/src/mainboard/asrock/e350m1/agesawrapper.h b/src/mainboard/asrock/e350m1/agesawrapper.h
index e45d09f240..6d7d9cd196 100644
--- a/src/mainboard/asrock/e350m1/agesawrapper.h
+++ b/src/mainboard/asrock/e350m1/agesawrapper.h
@@ -86,6 +86,7 @@ UINT32 agesawrapper_amdinitmid (void);
 UINT32 agesawrapper_amdreadeventlog (void);
 UINT32 agesawrapper_amdinitmmio (void);
 UINT32 agesawrapper_amdinitcpuio (void);
+UINT32 agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
 void *agesawrapper_getlateinitptr (int pick);
 
 #endif
diff --git a/src/mainboard/asrock/e350m1/platform_cfg.h b/src/mainboard/asrock/e350m1/platform_cfg.h
index 326765162e..a0cbd118f9 100644
--- a/src/mainboard/asrock/e350m1/platform_cfg.h
+++ b/src/mainboard/asrock/e350m1/platform_cfg.h
@@ -36,14 +36,16 @@
  * bigger than 1M you have to set the ROM size outside CIMx module and
  * before AGESA module get call.
  */
-#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1
-  #define BIOS_SIZE BIOS_SIZE_1M
-#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1
-  #define BIOS_SIZE BIOS_SIZE_2M
-#elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1
-  #define BIOS_SIZE BIOS_SIZE_4M
-#elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1
-  #define BIOS_SIZE BIOS_SIZE_8M
+#ifndef BIOS_SIZE
+  #if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1
+	#define BIOS_SIZE BIOS_SIZE_1M
+  #elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1
+	#define BIOS_SIZE BIOS_SIZE_2M
+  #elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1
+	#define BIOS_SIZE BIOS_SIZE_4M
+  #elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1
+	#define BIOS_SIZE BIOS_SIZE_8M
+  #endif
 #endif
 
 /**
@@ -56,7 +58,7 @@
 
 /**
  * @def SB_HPET_TIMER
- * @breif
+ * @brief
  *  0 - Disable hpet
  *  1 - Enable  hpet
  */
@@ -79,7 +81,7 @@
 
 /**
  * @def PCI_CLOCK_CTRL
- * @breif bit[0-4] used for PCI Slots Clock Control,
+ * @brief bit[0-4] used for PCI Slots Clock Control,
  *   0 - disable
  *   1 - enable
  *  PCI SLOT 0 define at BIT0
@@ -92,26 +94,26 @@
 
 /**
  * @def SATA_CONTROLLER
- * @breif INCHIP Sata Controller
+ * @brief INCHIP Sata Controller
  */
 #define SATA_CONTROLLER		CIMX_OPTION_ENABLED
 
 /**
  * @def SATA_MODE
- * @breif INCHIP Sata Controller Mode
+ * @brief INCHIP Sata Controller Mode
  *   NOTE: DO NOT ALLOW SATA & IDE use same mode
  */
 #define SATA_MODE			NATIVE_IDE_MODE
 
 /**
- * @breif INCHIP Sata IDE Controller Mode
+ * @brief INCHIP Sata IDE Controller Mode
  */
 #define IDE_LEGACY_MODE			0
 #define IDE_NATIVE_MODE			1
 
 /**
  * @def SATA_IDE_MODE
- * @breif INCHIP Sata IDE Controller Mode
+ * @brief INCHIP Sata IDE Controller Mode
  *   NOTE: DO NOT ALLOW SATA & IDE use same mode
  */
 #define SATA_IDE_MODE			IDE_LEGACY_MODE
@@ -155,7 +157,7 @@
 #define AZALIA_ENABLE			2
 
 /**
- * @breif INCHIP HDA controller
+ * @brief INCHIP HDA controller
  */
 #define AZALIA_CONTROLLER		AZALIA_AUTO