mb/starlabs/labtop: Configure tcc_offset based on power_profile settings
Set tcc_offset value based on the power_profile value, ranging from 10 to 20 degrees. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I66fb266c1730833ff6e2dbf8ea39f23ee0878590 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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@ -32,9 +32,6 @@ chip soc/intel/cannonlake
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register "PchPmSlpSusMinAssert" = "3" # 500ms
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register "PchPmSlpAMinAssert" = "3" # 2s
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# Thermal
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register "tcc_offset" = "10"
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# PM Util
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# GPE configuration
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# Note that GPE events called out in ASL code rely on this
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@ -17,19 +17,22 @@ void devtree_update(void)
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struct device *nic_dev = pcidev_on_root(0x14, 3);
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/* Update PL1 & PL2 based on CMOS settings */
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switch (get_uint_option("power_profile", 0)) {
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case 1:
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soc_conf->tdp_pl1_override = 17;
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soc_conf->tdp_pl2_override = 20;
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break;
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case 2:
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soc_conf->tdp_pl1_override = 20;
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soc_conf->tdp_pl2_override = 25;
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break;
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default:
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switch (get_power_profile(PP_POWER_SAVER)) {
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case PP_POWER_SAVER:
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disable_turbo();
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soc_conf->tdp_pl1_override = 15;
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soc_conf->tdp_pl2_override = 15;
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soc_conf->tdp_pl1_override = 15;
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soc_conf->tdp_pl2_override = 15;
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cfg->tcc_offset = 20;
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break;
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case PP_BALANCED:
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soc_conf->tdp_pl1_override = 17;
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soc_conf->tdp_pl2_override = 20;
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cfg->tcc_offset = 15;
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break;
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case PP_PERFORMANCE:
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soc_conf->tdp_pl1_override = 20;
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soc_conf->tdp_pl2_override = 25;
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cfg->tcc_offset = 10;
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break;
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}
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@ -38,9 +38,6 @@ chip soc/intel/tigerlake
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register "PchPmSlpSusMinAssert" = "3" # 500ms
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register "PchPmSlpAMinAssert" = "3" # 2s
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# Thermal
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register "tcc_offset" = "10"
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# PM Util
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# GPE configuration
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# Note that GPE events called out in ASL code rely on this
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@ -27,22 +27,25 @@ void devtree_update(void)
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switch (get_power_profile(PP_POWER_SAVER)) {
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case PP_POWER_SAVER:
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disable_turbo();
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soc_conf_2core->tdp_pl1_override = 15;
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soc_conf_4core->tdp_pl1_override = 15;
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soc_conf_2core->tdp_pl2_override = 15;
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soc_conf_4core->tdp_pl2_override = 15;
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soc_conf_2core->tdp_pl1_override = 15;
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soc_conf_4core->tdp_pl1_override = 15;
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soc_conf_2core->tdp_pl2_override = 15;
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soc_conf_4core->tdp_pl2_override = 15;
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cfg->tcc_offset = 20;
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break;
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case PP_BALANCED:
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soc_conf_2core->tdp_pl1_override = 15;
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soc_conf_4core->tdp_pl1_override = 15;
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soc_conf_2core->tdp_pl2_override = 25;
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soc_conf_4core->tdp_pl2_override = 25;
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soc_conf_2core->tdp_pl1_override = 15;
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soc_conf_4core->tdp_pl1_override = 15;
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soc_conf_2core->tdp_pl2_override = 25;
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soc_conf_4core->tdp_pl2_override = 25;
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cfg->tcc_offset = 15;
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break;
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case PP_PERFORMANCE:
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soc_conf_2core->tdp_pl1_override = 28;
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soc_conf_4core->tdp_pl1_override = 28;
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soc_conf_2core->tdp_pl2_override = 40;
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soc_conf_4core->tdp_pl2_override = 40;
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soc_conf_2core->tdp_pl1_override = 28;
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soc_conf_4core->tdp_pl1_override = 28;
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soc_conf_2core->tdp_pl2_override = 40;
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soc_conf_4core->tdp_pl2_override = 40;
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cfg->tcc_offset = 10;
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break;
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}
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