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mb/starlabs/labtop: Configure tcc_offset based on power_profile settings 

Set tcc_offset value based on the power_profile value, ranging from 10
to 20 degrees.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I66fb266c1730833ff6e2dbf8ea39f23ee0878590
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Sean Rhodes 2022-05-26 21:04:10 +01:00 committed by Felix Held
parent 49d0204c31
commit 99d2d62fa1
4 changed files with 30 additions and 30 deletions
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3
src/mainboard/starlabs/labtop/variants/cml/devicetree.cb
View File

@ -32,9 +32,6 @@ chip soc/intel/cannonlake
register "PchPmSlpSusMinAssert" = "3" # 500ms register "PchPmSlpSusMinAssert" = "3" # 500ms
register "PchPmSlpAMinAssert" = "3" # 2s register "PchPmSlpAMinAssert" = "3" # 2s
# Thermal
register "tcc_offset" = "10"
# PM Util # PM Util
# GPE configuration # GPE configuration
# Note that GPE events called out in ASL code rely on this # Note that GPE events called out in ASL code rely on this

23
src/mainboard/starlabs/labtop/variants/cml/devtree.c
View File

@ -17,19 +17,22 @@ void devtree_update(void)
struct device *nic_dev = pcidev_on_root(0x14, 3); struct device *nic_dev = pcidev_on_root(0x14, 3);
/* Update PL1 & PL2 based on CMOS settings */ /* Update PL1 & PL2 based on CMOS settings */
switch (get_uint_option("power_profile", 0)) { switch (get_power_profile(PP_POWER_SAVER)) {
case 1: case PP_POWER_SAVER:
soc_conf->tdp_pl1_override = 17;
soc_conf->tdp_pl2_override = 20;
break;
case 2:
soc_conf->tdp_pl1_override = 20;
soc_conf->tdp_pl2_override = 25;
break;
default:
disable_turbo(); disable_turbo();
soc_conf->tdp_pl1_override = 15; soc_conf->tdp_pl1_override = 15;
soc_conf->tdp_pl2_override = 15; soc_conf->tdp_pl2_override = 15;
cfg->tcc_offset = 20;
break;
case PP_BALANCED:
soc_conf->tdp_pl1_override = 17;
soc_conf->tdp_pl2_override = 20;
cfg->tcc_offset = 15;
break;
case PP_PERFORMANCE:
soc_conf->tdp_pl1_override = 20;
soc_conf->tdp_pl2_override = 25;
cfg->tcc_offset = 10;
break; break;
} }

3
src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb
View File

@ -38,9 +38,6 @@ chip soc/intel/tigerlake
register "PchPmSlpSusMinAssert" = "3" # 500ms register "PchPmSlpSusMinAssert" = "3" # 500ms
register "PchPmSlpAMinAssert" = "3" # 2s register "PchPmSlpAMinAssert" = "3" # 2s
# Thermal
register "tcc_offset" = "10"
# PM Util # PM Util
# GPE configuration # GPE configuration
# Note that GPE events called out in ASL code rely on this # Note that GPE events called out in ASL code rely on this

3
src/mainboard/starlabs/labtop/variants/tgl/devtree.c
View File

@ -31,18 +31,21 @@ void devtree_update(void)
soc_conf_4core->tdp_pl1_override = 15; soc_conf_4core->tdp_pl1_override = 15;
soc_conf_2core->tdp_pl2_override = 15; soc_conf_2core->tdp_pl2_override = 15;
soc_conf_4core->tdp_pl2_override = 15; soc_conf_4core->tdp_pl2_override = 15;
cfg->tcc_offset = 20;
break; break;
case PP_BALANCED: case PP_BALANCED:
soc_conf_2core->tdp_pl1_override = 15; soc_conf_2core->tdp_pl1_override = 15;
soc_conf_4core->tdp_pl1_override = 15; soc_conf_4core->tdp_pl1_override = 15;
soc_conf_2core->tdp_pl2_override = 25; soc_conf_2core->tdp_pl2_override = 25;
soc_conf_4core->tdp_pl2_override = 25; soc_conf_4core->tdp_pl2_override = 25;
cfg->tcc_offset = 15;
break; break;
case PP_PERFORMANCE: case PP_PERFORMANCE:
soc_conf_2core->tdp_pl1_override = 28; soc_conf_2core->tdp_pl1_override = 28;
soc_conf_4core->tdp_pl1_override = 28; soc_conf_4core->tdp_pl1_override = 28;
soc_conf_2core->tdp_pl2_override = 40; soc_conf_2core->tdp_pl2_override = 40;
soc_conf_4core->tdp_pl2_override = 40; soc_conf_4core->tdp_pl2_override = 40;
cfg->tcc_offset = 10;
break; break;
} }