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baytrail: don't allow PCIE wake ups 

The PCIe subsystem was constantly waking up boards from
S3 and S5. Completely disable PCIe wake ups. It can be made
mainboard-configurable later if needed.

BUG=chrome-os-partner:24004
BRANCH=None
TEST=Both S3 and EC RW->RW update (trip through S5) don't
     cause wakeups.

Change-Id: I922e2947c4b6e29277d913f06192601a2954f8fe
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176791
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4972
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This commit is contained in:
Aaron Durbin 2013-11-14 11:06:17 -06:00 committed by Kyösti Mälkki
parent 281abfb2db
commit 99d8818af3
1 changed files with 2 additions and 2 deletions
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4
src/soc/intel/baytrail/smm.c
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@ -93,8 +93,8 @@ void southcluster_smm_enable_smi(void)
{ {
printk(BIOS_DEBUG, "Enabling SMIs.\n"); printk(BIOS_DEBUG, "Enabling SMIs.\n");
/* Configure events */ /* Configure events Disable pcie wake. */
enable_pm1(PWRBTN_EN | GBL_EN); enable_pm1(PWRBTN_EN | GBL_EN | PCIEXPWAK_DIS);
disable_gpe(PME_B0_EN); disable_gpe(PME_B0_EN);
/* Set up the GPIO route. */ /* Set up the GPIO route. */