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soc/intel/common: Rename cse_is_hfs3_fw_sku_custom() 

Rename cse_is_hfs3_fw_sku_custom() to cse_is_hfs3_fw_sku_lite() and
rename custom_bp.c to cse_lite.c. Also, rename all CSE Custom SKU
references to CSE Lite SKU.

TEST=Verified on hatch

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I20654bc14f0da8d21e31a4183df7a2e34394f34e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
This commit is contained in:
Sridhar Siricilla 2020-05-12 21:05:04 +05:30 committed by Furquan Shaikh
parent 17b4803381
commit 99dbca381b
5 changed files with 22 additions and 22 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/soc/intel/common/block/cse/Kconfig
View File

@ -13,9 +13,9 @@ config SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_IN_SMM
Use this config to include common CSE block to make HECI function
disable in SMM mode
config SOC_INTEL_CSE_CUSTOM_SKU
config SOC_INTEL_CSE_LITE_SKU
bool
default n
depends on CHROMEOS
help
Enables CSE Custom SKU
Enables CSE Lite SKU

2
src/soc/intel/common/block/cse/Makefile.inc
View File

@ -1,5 +1,5 @@
bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c
romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c
ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c
ramstage-$(CONFIG_SOC_INTEL_CSE_CUSTOM_SKU) += custom_bp.c
ramstage-$(CONFIG_SOC_INTEL_CSE_LITE_SKU) += cse_lite.c
smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_IN_SMM) += disable_heci.c

16
src/soc/intel/common/block/cse/cse.c
View File

@ -258,11 +258,11 @@ bool cse_is_hfs1_com_soft_temp_disable(void)
return cse_check_hfs1_com(ME_HFS1_COM_SOFT_TEMP_DISABLE);
}
bool cse_is_hfs3_fw_sku_custom(void)
bool cse_is_hfs3_fw_sku_lite(void)
{
union me_hfsts3 hfs3;
hfs3.data = me_read_config32(PCI_ME_HFSTS3);
return hfs3.fields.fw_sku == ME_HFS3_FW_SKU_CUSTOM;
return hfs3.fields.fw_sku == ME_HFS3_FW_SKU_LITE;
}
/* Makes the host ready to communicate with CSE */
@ -600,7 +600,7 @@ static bool cse_is_global_reset_allowed(void)
* - CSE's current working state is Normal and current operation mode is Normal.
* - (or) CSE's current working state is normal and current operation mode can
* be Soft Temp Disable or Security Override Mode if CSE's Firmware SKU is
* Custom.
* Lite.
*/
if (!cse_is_hfs1_cws_normal())
return false;
@ -608,7 +608,7 @@ static bool cse_is_global_reset_allowed(void)
if (cse_is_hfs1_com_normal())
return true;
if (cse_is_hfs3_fw_sku_custom()) {
if (cse_is_hfs3_fw_sku_lite()) {
if (cse_is_hfs1_com_soft_temp_disable() || cse_is_hfs1_com_secover_mei_msg())
return true;
}
@ -669,7 +669,7 @@ static bool cse_is_hmrfpo_enable_allowed(void)
* Allow sending HMRFPO ENABLE command only if:
* - CSE's current working state is Normal and current operation mode is Normal
* - (or) cse's current working state is normal and current operation mode is
* Soft Temp Disable if CSE's Firmware SKU is Custom
* Soft Temp Disable if CSE's Firmware SKU is Lite
*/
if (!cse_is_hfs1_cws_normal())
return false;
@ -677,7 +677,7 @@ static bool cse_is_hmrfpo_enable_allowed(void)
if (cse_is_hfs1_com_normal())
return true;
if (cse_is_hfs3_fw_sku_custom() && cse_is_hfs1_com_soft_temp_disable())
if (cse_is_hfs3_fw_sku_lite() && cse_is_hfs1_com_soft_temp_disable())
return true;
return false;
@ -818,10 +818,10 @@ void print_me_fw_version(void *unused)
return;
/*
* Ignore if ME Firmware SKU type is custom since
* Ignore if ME Firmware SKU type is Lite since
* print_boot_partition_info() logs RO(BP1) and RW(BP2) versions.
*/
if (cse_is_hfs3_fw_sku_custom())
if (cse_is_hfs3_fw_sku_lite())
return;
/*

12
src/soc/intel/common/block/cse/custom_bp.c → src/soc/intel/common/block/cse/cse_lite.c
View File

@ -10,16 +10,16 @@
#define GET_BP_STR(bp_index) (bp_index ? "RW" : "RO")
/*
* CSE Firmware supports 3 boot partitions. For CSE Custom SKU, only 2 boot partitions are
* CSE Firmware supports 3 boot partitions. For CSE Lite SKU, only 2 boot partitions are
* used and 3rd boot partition is set to BP_STATUS_PARTITION_NOT_PRESENT.
* CSE Custom SKU Image Layout:
* CSE Lite SKU Image Layout:
* ------------- ------------------- ---------------------
* |CSE REGION | => | RO | RW | DATA | => | BP1 | BP2 | DATA |
* ------------- ------------------- ---------------------
*/
#define CSE_MAX_BOOT_PARTITIONS 3
/* CSE Custom SKU's valid bootable partition identifiers */
/* CSE Lite SKU's valid bootable partition identifiers */
enum boot_partition_id {
/* RO(BP1) contains recovery/minimal boot FW */
RO = 0,
@ -299,9 +299,9 @@ void cse_fw_sync(void *unused)
return;
}
/* If CSE SKU type is not Custom, skip enabling CSE Custom SKU */
if (!cse_is_hfs3_fw_sku_custom()) {
printk(BIOS_ERR, "cse_bp: Not a CSE Custom SKU\n");
/* If CSE SKU type is not Lite, skip enabling CSE Lite SKU */
if (!cse_is_hfs3_fw_sku_lite()) {
printk(BIOS_ERR, "cse_bp: Not a CSE Lite SKU\n");
return;
}

10
src/soc/intel/common/block/include/intelblocks/cse.h
View File

@ -40,7 +40,7 @@
/* ME Firmware SKU Types */
#define ME_HFS3_FW_SKU_CONSUMER 0x2
#define ME_HFS3_FW_SKU_CORPORATE 0x3
#define ME_HFS3_FW_SKU_CUSTOM 0x5
#define ME_HFS3_FW_SKU_LITE 0x5
/* HFSTS register offsets in PCI config space */
enum {
@ -201,10 +201,10 @@ bool cse_is_hfs1_com_secover_mei_msg(void);
bool cse_is_hfs1_com_soft_temp_disable(void);
/*
* Checks CSE's Firmware SKU is Custom or not.
* Returns true if CSE's Firmware SKU is Custom, otherwise false
* Checks CSE's Firmware SKU is Lite or not.
* Returns true if CSE's Firmware SKU is Lite, otherwise false
*/
bool cse_is_hfs3_fw_sku_custom(void);
bool cse_is_hfs3_fw_sku_lite(void);
/*
* Polls for CSE's current operation mode 'Soft Temp Disable'.
@ -213,7 +213,7 @@ bool cse_is_hfs3_fw_sku_custom(void);
uint8_t cse_wait_com_soft_temp_disable(void);
/*
* The CSE Custom SKU supports notion of RO and RW boot partitions. The function will set
* The CSE Lite SKU supports notion of RO and RW boot partitions. The function will set
* CSE's boot partition as per Chrome OS boot modes. In normal mode, the function allows CSE to
* boot from RW and triggers recovery mode if CSE fails to jump to RW.
* In software triggered recovery mode, the function allows CSE to boot from whatever is