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northbridge/amd/amdfam10: Limit maximum RAM clock to BKDG recommendations 

Change-Id: I45eb03a4b351e458e8448245896743bd6fa57637
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11943
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Timothy Pearson 2015-09-05 18:00:27 -05:00 committed by Kyösti Mälkki
parent b8a355dcdf
commit 99e1a672ec
2 changed files with 47 additions and 7 deletions
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44
src/northbridge/amd/amdfam10/raminit_amdmct.c
View File

@ -42,30 +42,59 @@ static void print_tf(const char *func, const char *strval)
#endif
}
static uint16_t mct_MaxLoadFreq(uint8_t count, uint16_t freq)
static uint16_t mct_MaxLoadFreq(uint8_t count, uint8_t registered, uint16_t freq)
{
/* Return limited maximum RAM frequency */
if (IS_ENABLED(CONFIG_DIMM_DDR2)) {
if (IS_ENABLED(CONFIG_DIMM_REGISTERED)) {
if (IS_ENABLED(CONFIG_DIMM_REGISTERED) && registered) {
/* K10 BKDG Rev. 3.62 Table 53 */
if (count > 2) {
/* Limit to DDR2-533 */
if (freq > 266) {
freq = 266;
print_tf(__func__, ": More than 2 DIMMs on channel; limiting to DDR2-533\n");
print_tf(__func__, ": More than 2 registered DIMMs on channel; limiting to DDR2-533\n");
}
}
}
else {
} else {
/* K10 BKDG Rev. 3.62 Table 52 */
if (count > 1) {
/* Limit to DDR2-800 */
if (freq > 400) {
freq = 400;
print_tf(__func__, ": More than 1 DIMM on channel; limiting to DDR2-800\n");
print_tf(__func__, ": More than 1 unbuffered DIMM on channel; limiting to DDR2-800\n");
}
}
}
} else if (IS_ENABLED(CONFIG_DIMM_DDR3)) {
if (IS_ENABLED(CONFIG_DIMM_REGISTERED) && registered) {
/* K10 BKDG Rev. 3.62 Table 34 */
if (count > 2) {
/* Limit to DDR3-800 */
if (freq > 400) {
freq = 400;
print_tf(__func__, ": More than 2 registered DIMMs on channel; limiting to DDR3-800\n");
}
} else if (count == 2) {
/* Limit to DDR3-1066 */
if (freq > 533) {
freq = 533;
print_tf(__func__, ": 2 registered DIMMs on channel; limiting to DDR3-1066\n");
}
} else {
/* Limit to DDR3-1333 */
if (freq > 666) {
freq = 666;
print_tf(__func__, ": 1 registered DIMM on channel; limiting to DDR3-1333\n");
}
}
} else {
/* K10 BKDG Rev. 3.62 Table 33 */
/* Limit to DDR3-1333 */
if (freq > 666) {
freq = 666;
print_tf(__func__, ": unbuffered DIMMs on channel; limiting to DDR3-1333\n");
}
}
}
return freq;
@ -118,6 +147,9 @@ static uint16_t mct_MaxLoadFreq(uint8_t count, uint16_t freq)
//C32
#elif CONFIG_CPU_SOCKET_TYPE == 0x14
#include "../amdmct/mct_ddr3/mctardk5.c"
//G34
#elif CONFIG_CPU_SOCKET_TYPE == 0x15
#include "../amdmct/mct_ddr3/mctardk5.c"
#endif
#else /* DDR2 */

10
src/northbridge/amd/amdmct/wrappers/mcti_d.c
View File

@ -301,6 +301,8 @@ static void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat)
/* Determine the number of installed DIMMs */
int ch1_count = 0;
int ch2_count = 0;
uint8_t ch1_registered = 0;
uint8_t ch2_registered = 0;
int i;
for (i = 0; i < 15; i = i + 2) {
if (pDCTstat->DIMMValid & (1 << i))
@ -308,13 +310,19 @@ static void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat)
if (pDCTstat->DIMMValid & (1 << (i + 1)))
ch2_count++;
}
for (i = 0; i < MAX_DIMMS_SUPPORTED; i = i + 2) {
if (pDCTstat->DimmRegistered[i])
ch1_registered = 1;
if (pDCTstat->DimmRegistered[i + 1])
ch2_registered = 1;
}
if (IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)) {
printk(BIOS_DEBUG, "mctGet_MaxLoadFreq: Channel 1: %d DIMM(s) detected\n", ch1_count);
printk(BIOS_DEBUG, "mctGet_MaxLoadFreq: Channel 2: %d DIMM(s) detected\n", ch2_count);
}
/* Set limits if needed */
pDCTstat->PresetmaxFreq = mct_MaxLoadFreq(max(ch1_count, ch2_count), pDCTstat->PresetmaxFreq);
pDCTstat->PresetmaxFreq = mct_MaxLoadFreq(max(ch1_count, ch2_count), (ch1_registered || ch2_registered), pDCTstat->PresetmaxFreq);
}
#ifdef UNUSED_CODE