From 99fd2a3b3ac587498b551c2c6e5d6d20f646e65b Mon Sep 17 00:00:00 2001 From: Marc Jones Date: Thu, 14 May 2009 23:42:41 +0000 Subject: [PATCH] Update equivalent processor revision ID to load latest microcode patches and register setting for all FAM10 processors. This does not include new errata for FAM10 C2. Signed-off-by: Marc Jones Acked-by: Vincent Lim (vincent.lim@amd.com) git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4288 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/cpu/amd/model_10xxx/defaults.h | 110 +++++++++--------- src/cpu/amd/model_10xxx/update_microcode.c | 12 +- .../amd/serengeti_cheetah_fam10/Options.lb | 9 +- src/mainboard/tyan/s2912_fam10/Options.lb | 9 +- src/northbridge/amd/amdfam10/raminit_amdmct.c | 3 + src/northbridge/amd/amdmct/amddefs.h | 3 + 6 files changed, 78 insertions(+), 68 deletions(-) diff --git a/src/cpu/amd/model_10xxx/defaults.h b/src/cpu/amd/model_10xxx/defaults.h index 2497c5ba8e..5fc1e66a29 100644 --- a/src/cpu/amd/model_10xxx/defaults.h +++ b/src/cpu/amd/model_10xxx/defaults.h @@ -30,23 +30,23 @@ static const struct { u32 mask_lo; u32 mask_hi; } fam10_msr_default[] = { - { TOP_MEM2, AMD_DR_ALL, AMD_PTYPE_ALL, + { TOP_MEM2, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF }, - { SYSCFG, AMD_DR_ALL, AMD_PTYPE_ALL, + { SYSCFG, AMD_FAM10_ALL, AMD_PTYPE_ALL, 3 << 21, 0x00000000, 3 << 21, 0x00000000 }, /* [MtrrTom2En]=1,[TOM2EnWB] = 1*/ - { HWCR, AMD_DR_ALL, AMD_PTYPE_ALL, + { HWCR, AMD_FAM10_ALL, AMD_PTYPE_ALL, 1 << 4, 0x00000000, 1 << 4, 0x00000000 }, /* [INVD_WBINVD]=1 */ - { MC4_CTL_MASK, AMD_DR_ALL, AMD_PTYPE_ALL, + { MC4_CTL_MASK, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0xF << 19, 0x00000000, 0xF << 19, 0x00000000 }, /* [RtryHt[0..3]]=1 */ - { DC_CFG, AMD_DR_ALL, AMD_PTYPE_SVR, + { DC_CFG, AMD_FAM10_ALL, AMD_PTYPE_SVR, 0x00000000, 0x00000004, 0x00000000, 0x0000000C }, /* [REQ_CTR] = 1 for Server */ @@ -54,7 +54,7 @@ static const struct { 0x00000000, 0x00000000, 0x00000000, 0x00000C00 }, /* Errata 326 */ - { NB_CFG, AMD_DR_ALL, AMD_PTYPE_DC | AMD_PTYPE_MC, + { NB_CFG, AMD_FAM10_ALL, AMD_PTYPE_DC | AMD_PTYPE_MC, 0x00000000, 1 << 22, 0x00000000, 1 << 22 }, /* [ApicInitIDLo]=1 */ @@ -62,15 +62,15 @@ static const struct { 1 << 29, 0x00000000, 1 << 29, 0x00000000 }, /* For Bx Smash1GPages=1 */ - { DC_CFG, AMD_DR_ALL, AMD_PTYPE_ALL, + { DC_CFG, AMD_FAM10_ALL, AMD_PTYPE_ALL, 1 << 24, 0x00000000, 1 << 24, 0x00000000 }, /* Erratum #261 [DIS_PIGGY_BACK_SCRUB]=1 */ - { LS_CFG, AMD_DR_GT_B0, AMD_PTYPE_ALL, + { LS_CFG, AMD_FAM10_GT_B0, AMD_PTYPE_ALL, 0 << 1, 0x00000000, 1 << 1, 0x00000000 }, /* IDX_MATCH_ALL=0 */ - { BU_CFG, AMD_DR_GT_B0, AMD_PTYPE_ALL, + { BU_CFG, AMD_DR_LT_B3, AMD_PTYPE_ALL, 1 << 21, 0x00000000, 1 << 21, 0x00000000 }, /* Erratum #254 DR B1 BU_CFG[21]=1 */ @@ -79,11 +79,11 @@ static const struct { 1 << 23, 0x00000000 }, /* Erratum #309 BU_CFG[23]=1 */ /* CPUID_EXT_FEATURES */ - { CPUIDFEATURES, AMD_DR_ALL, AMD_PTYPE_DC | AMD_PTYPE_MC, + { CPUIDFEATURES, AMD_FAM10_ALL, AMD_PTYPE_DC | AMD_PTYPE_MC, 1 << 28, 0x00000000, 1 << 28, 0x00000000 }, /* [HyperThreadFeatEn]=1 */ - { CPUIDFEATURES, AMD_DR_ALL, AMD_PTYPE_DC, + { CPUIDFEATURES, AMD_FAM10_ALL, AMD_PTYPE_DC, 0x00000000, 1 << (33-32), 0x00000000, 1 << (33-32) }, /* [ExtendedFeatEn]=1 */ }; @@ -103,7 +103,7 @@ static const struct { /* Function 0 - HT Config */ - { 0, 0x68, AMD_DR_ALL, AMD_PTYPE_ALL, + { 0, 0x68, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x004E4800, 0x006E6800 }, /* [19:17] for 8bit APIC config, [14:13] BufPriRel = 2h [11] RspPassPW set, [22:21] DsNpReqLmt = 10b */ @@ -112,20 +112,20 @@ static const struct { { 0, 0x68, (AMD_DR_B0 | AMD_DR_B1), AMD_PTYPE_SVR, 0x00200000, 0x00600000 }, /* [22:21] DsNpReqLmt0 = 01b */ - { 0, 0x84, AMD_DR_ALL, AMD_PTYPE_ALL, + { 0, 0x84, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x00002000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */ - { 0, 0xA4, AMD_DR_ALL, AMD_PTYPE_ALL, + { 0, 0xA4, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x00002000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */ - { 0, 0xC4, AMD_DR_ALL, AMD_PTYPE_ALL, + { 0, 0xC4, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x00002000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */ - { 0, 0xE4, AMD_DR_ALL, AMD_PTYPE_ALL, + { 0, 0xE4, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x00002000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */ /* Link Global Extended Control Register */ - { 0, 0x16C, AMD_DR_ALL, AMD_PTYPE_ALL, + { 0, 0x16C, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x0000C000, 0x0000E000 }, /* [15:13] ForceFullT0 = 110b */ /* Function 1 - Map Init */ @@ -137,25 +137,25 @@ static const struct { * Array MCA errors. BKDG Doc #3116 Rev 1.07 */ - { 1, 0x110, AMD_DR_ALL, AMD_PTYPE_ALL, + { 1, 0x110, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x20000000, 0xFFFFFFFF }, /* Select extended MMIO Base */ - { 1, 0x114, AMD_DR_ALL, AMD_PTYPE_ALL, + { 1, 0x114, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x00000000, 0xFFFFFFFF }, /* Clear map */ - { 1, 0x110, AMD_DR_ALL, AMD_PTYPE_ALL, + { 1, 0x110, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x30000000, 0xFFFFFFFF }, /* Select extended MMIO Base */ - { 1, 0x114, AMD_DR_ALL, AMD_PTYPE_ALL, + { 1, 0x114, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x00000000, 0xFFFFFFFF }, /* Clear map */ /* Function 2 - DRAM Controller */ /* Function 3 - Misc. Control */ - { 3, 0x40, AMD_DR_ALL, AMD_PTYPE_ALL, + { 3, 0x40, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x00000100, 0x00000100 }, /* [8] MstrAbrtEn */ - { 3, 0x44, AMD_DR_ALL, AMD_PTYPE_ALL, + { 3, 0x44, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x4A30005C, 0x4A30005C }, /* [30] SyncOnDramAdrParErrEn = 1, [27] NbMcaToMstCpuEn = 1, [25] DisPciCfgCpuErrRsp = 1, @@ -167,42 +167,42 @@ static const struct { [2] SyncOnUcEccEn = 1 */ /* XBAR buffer settings */ - { 3, 0x6C, AMD_DR_ALL, AMD_PTYPE_ALL, + { 3, 0x6C, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x00018052, 0x700780F7 }, /* Errata 281 Workaround */ { 3, 0x6C, ( AMD_DR_B0 | AMD_DR_B1), AMD_PTYPE_SVR, 0x00010094, 0x700780F7 }, - { 3, 0x6C, AMD_DR_ALL, AMD_PTYPE_UMA, + { 3, 0x6C, AMD_FAM10_ALL, AMD_PTYPE_UMA, 0x60018051, 0x700780F7 }, - { 3, 0x70, AMD_DR_ALL, AMD_PTYPE_ALL, + { 3, 0x70, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x00041153, 0x777777F7 }, - { 3, 0x70, AMD_DR_ALL, AMD_PTYPE_UMA, + { 3, 0x70, AMD_FAM10_ALL, AMD_PTYPE_UMA, 0x61221151, 0x777777F7 }, - { 3, 0x74, AMD_DR_ALL, AMD_PTYPE_UMA, + { 3, 0x74, AMD_FAM10_ALL, AMD_PTYPE_UMA, 0x00080101, 0x000F7777 }, - { 3, 0x7C, AMD_DR_ALL, AMD_PTYPE_ALL, + { 3, 0x7C, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x00090914, 0x707FFF1F }, /* Errata 281 Workaround */ { 3, 0x7C, ( AMD_DR_B0 | AMD_DR_B1), AMD_PTYPE_SVR, 0x00144514, 0x707FFF1F }, - { 3, 0x7C, AMD_DR_ALL, AMD_PTYPE_UMA, + { 3, 0x7C, AMD_FAM10_ALL, AMD_PTYPE_UMA, 0x00070814, 0x007FFF1F }, - { 3, 0x140, AMD_DR_ALL, AMD_PTYPE_ALL, + { 3, 0x140, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x00800756, 0x00F3FFFF }, - { 3, 0x140, AMD_DR_ALL, AMD_PTYPE_UMA, + { 3, 0x140, AMD_FAM10_ALL, AMD_PTYPE_UMA, 0x00C37756, 0x00F3FFFF }, - { 3, 0x144, AMD_DR_ALL, AMD_PTYPE_UMA, + { 3, 0x144, AMD_FAM10_ALL, AMD_PTYPE_UMA, 0x00000036, 0x000000FF }, /* Errata 281 Workaround */ @@ -210,45 +210,45 @@ static const struct { AMD_PTYPE_SVR, 0x00000001, 0x0000000F }, /* [3:0] RspTok = 0001b */ - { 3, 0x148, AMD_DR_ALL, AMD_PTYPE_UMA, + { 3, 0x148, AMD_FAM10_ALL, AMD_PTYPE_UMA, 0x8000052A, 0xD5FFFFFF }, /* ACPI Power State Control Reg1 */ - { 3, 0x80, AMD_DR_ALL, AMD_PTYPE_ALL, + { 3, 0x80, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0xE6002200, 0xFFFFFFFF }, /* ACPI Power State Control Reg2 */ - { 3, 0x84, AMD_DR_ALL, AMD_PTYPE_ALL, + { 3, 0x84, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0xA0E641E6, 0xFFFFFFFF }, - { 3, 0xA0, AMD_DR_ALL, AMD_PTYPE_MOB | AMD_PTYPE_DSK, + { 3, 0xA0, AMD_FAM10_ALL, AMD_PTYPE_MOB | AMD_PTYPE_DSK, 0x00000080, 0x00000080 }, /* [7] PSIVidEnable */ - { 3, 0xA0, AMD_DR_ALL, AMD_PTYPE_ALL, + { 3, 0xA0, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x00001800, 0x000003800 }, /* [13:11] PllLockTime = 3 */ /* Reported Temp Control Register */ - { 3, 0xA4, AMD_DR_ALL, AMD_PTYPE_ALL, + { 3, 0xA4, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x00000080, 0x00000080 }, /* [7] TempSlewDnEn = 1 */ /* Clock Power/Timing Control 0 Register */ - { 3, 0xD4, AMD_DR_ALL, AMD_PTYPE_ALL, + { 3, 0xD4, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0xC0000F00, 0xF0000F00 }, /* [31] NbClkDivApplyAll = 1, [30:28] NbClkDiv = 100b,[11:8] ClkRampHystSel = 1111b */ /* Clock Power/Timing Control 1 Register */ - { 3, 0xD8, AMD_DR_ALL, AMD_PTYPE_ALL, + { 3, 0xD8, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x03000016, 0x0F000077 }, /* [6:4] VSRampTime = 1, [2:0] VSSlamTime = 6, [27:24] ReConDel = 3 */ /* Clock Power/Timing Control 2 Register */ - { 3, 0xDC, AMD_DR_ALL, AMD_PTYPE_ALL, + { 3, 0xDC, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x00005000, 0x00007000 }, /* [14:12] NbsynPtrAdj = 5 */ /* Extended NB MCA Config Register */ - { 3, 0x180, AMD_DR_ALL, AMD_PTYPE_ALL, + { 3, 0x180, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x007003E2, 0x007003E2 }, /* [22:20] = SyncFloodOn_Err = 7, [9] SyncOnUncNbAryEn = 1 , [8] SyncOnProtEn = 1, @@ -258,11 +258,11 @@ static const struct { [1] SyncFloodOnUsPwDataErr = 1 */ /* L3 Control Register */ - { 3, 0x1B8, AMD_DR_ALL, AMD_PTYPE_ALL, + { 3, 0x1B8, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x00001000, 0x00001000 }, /* [12] = L3PrivReplEn */ /* IBS Control Register */ - { 3, 0x1CC, AMD_DR_ALL, AMD_PTYPE_ALL, + { 3, 0x1CC, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x00000100, 0x00000100 }, /* [8] = LvtOffsetVal */ }; @@ -279,40 +279,40 @@ static const struct { u32 mask; } fam10_htphy_default[] = { - { 0x520A, AMD_DR_Bx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x520A, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00004400, 0x00006400 }, /* HT_PHY_DLL_REG */ - { 0x530A, AMD_DR_Bx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x530A, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00004400, 0x00006400 }, /* HT_PHY_DLL_REG */ - { 0xCF, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0xCF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000000, 0x000000FF }, /* Provide clear setting for logical completeness */ - { 0xDF, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0xDF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000000, 0x000000FF }, /* Provide clear setting for logical completeness */ - { 0xCF, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, + { 0xCF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, 0x0000006D, 0x000000FF }, /* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */ - { 0xDF, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, + { 0xDF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, 0x0000006D, 0x000000FF }, /* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */ /* Link Phy Receiver Loop Filter Registers */ - { 0xD1, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, + { 0xD1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, 0x08040000, 0x3FFFC000 }, /* [29:22] LfcMax = 20h, [21:14] LfcMin = 10h */ - { 0xC1, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, + { 0xC1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, 0x08040000, 0x3FFFC000 }, /* [29:22] LfcMax = 20h, [21:14] LfcMin = 10h */ - { 0xD1, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, + { 0xD1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, 0x04020000, 0x3FFFC000 }, /* [29:22] LfcMax = 10h, [21:14] LfcMin = 08h */ - { 0xC1, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, + { 0xC1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, 0x04020000, 0x3FFFC000 }, /* [29:22] LfcMax = 10h, [21:14] LfcMin = 08h */ }; diff --git a/src/cpu/amd/model_10xxx/update_microcode.c b/src/cpu/amd/model_10xxx/update_microcode.c index 8b61a6e5df..f7f717d110 100644 --- a/src/cpu/amd/model_10xxx/update_microcode.c +++ b/src/cpu/amd/model_10xxx/update_microcode.c @@ -39,11 +39,12 @@ static const u8 microcode_updates[] __attribute__ ((aligned(16))) = { * 00100F00h 1000h 01000020h * 00100F01h 1000h 01000020h * 00100F02h 1000h 01000020h - * 00100F20h 1020h 01000084h - * 00100F21h 1020h 01000084h - * 00100F2Ah 1020h 01000084h - * 00100F22h 1022h 01000083h - * 00100F23h 1022h 01000083h + * 00100F20h 1020h 01000096h + * 00100F21h (DR-B1) 1020h 01000096h + * 00100F2Ah (DR-BA) 1020h 01000096h + * 00100F22h (DR-B2) 1022h 01000095h + * 00100F23h (DR-B3) 1022h 01000095h + * 00100F62h (DA-C2) 1062h 0100009Fh */ #include AMD_UCODE_PATCH_FILE @@ -66,6 +67,7 @@ static u32 get_equivalent_processor_rev_id(u32 orig_id) { 0x100f2A, 0x1020, 0x100f22, 0x1022, 0x100f23, 0x1022, + 0x100f62, 0x1062, }; u32 new_id; diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb b/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb index 8bf43bb656..80dff3a67a 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb +++ b/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb @@ -261,11 +261,12 @@ default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80 ## ## Set microcode patch file name ## -## Barcelona rev Ax: "mc_patch_01000020.h" -## Barcelona rev B0, B1, BA: "mc_patch_01000084.h" -## Barcelona rev B2, B3: "mc_patch_01000083.h" +## Barcelona rev DR-Ax: "mc_patch_01000020.h" +## Barcelona rev DR-B0, B1, BA: "mc_patch_01000096.h" +## Barcelona rev DR-B2, B3: "mc_patch_01000095.h" +## Shanghai rev DA-C2: "mc_patch_0100009f.h" ## -default AMD_UCODE_PATCH_FILE="mc_patch_01000083.h" +default AMD_UCODE_PATCH_FILE="mc_patch_01000095.h" ### ### coreboot layout values diff --git a/src/mainboard/tyan/s2912_fam10/Options.lb b/src/mainboard/tyan/s2912_fam10/Options.lb index 0e9b91ce38..0f77329e6b 100644 --- a/src/mainboard/tyan/s2912_fam10/Options.lb +++ b/src/mainboard/tyan/s2912_fam10/Options.lb @@ -258,11 +258,12 @@ default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2912 ## ## Set microcode patch file name ## -## Barcelona rev Ax: "mc_patch_01000020.h" -## Barcelona rev B0, B1, BA: "mc_patch_01000084.h" -## Barcelona rev B2, B3: "mc_patch_01000083.h" +## Barcelona rev DR-Ax: "mc_patch_01000020.h" +## Barcelona rev DR-B0, B1, BA: "mc_patch_01000096.h" +## Barcelona rev DR-B2, B3: "mc_patch_01000095.h" +## Shanghai rev DA-C2: "mc_patch_0100009f.h" ## -default AMD_UCODE_PATCH_FILE="mc_patch_01000083.h" +default AMD_UCODE_PATCH_FILE="mc_patch_01000095.h" ### ### coreboot layout values diff --git a/src/northbridge/amd/amdfam10/raminit_amdmct.c b/src/northbridge/amd/amdfam10/raminit_amdmct.c index 9696689281..fd967b5ebf 100644 --- a/src/northbridge/amd/amdfam10/raminit_amdmct.c +++ b/src/northbridge/amd/amdfam10/raminit_amdmct.c @@ -149,6 +149,9 @@ u32 mctGetLogicalCPUID(u32 Node) case 0x10023: ret = AMD_DR_B3; break; + case 0x10062: + ret = AMD_RB_C2; + break; default: /* FIXME: mabe we should die() here. */ print_err("FIXME! CPU Version unknown or not supported! \n"); diff --git a/src/northbridge/amd/amdmct/amddefs.h b/src/northbridge/amd/amdmct/amddefs.h index 6ff9d02b34..5afb0a3c1d 100644 --- a/src/northbridge/amd/amdmct/amddefs.h +++ b/src/northbridge/amd/amdmct/amddefs.h @@ -40,6 +40,7 @@ #define AMD_DR_B2 0x00200000 /* Barcelona B2 */ #define AMD_DR_BA 0x00400000 /* Barcelona BA */ #define AMD_DR_B3 0x00800000 /* Barcelona B3 */ +#define AMD_RB_C2 0x01000000 /* Shanghai C2 */ /* * Groups - Create as many as you wish, from the above public values @@ -57,6 +58,8 @@ #define AMD_DR_LT_B3 (AMD_DR_B0 | AMD_DR_B1 | AMD_DR_B2 | AMD_DR_BA) #define AMD_DR_GT_B0 (AMD_DR_ALL & ~(AMD_DR_B0)) #define AMD_DR_ALL (AMD_DR_Bx) +#define AMD_FAM10_ALL (AMD_DR_ALL | AMD_RB_C2) +#define AMD_FAM10_GT_B0 (AMD_FAM10_ALL & ~(AMD_DR_B0)) /* * Public Platforms - USE THESE VERSIONS TO MAKE COMPARE WITH CPUPLATFORMTYPE RETURN VALUE