From 9a035ede17a23127ec4fc451ab84283e79636e75 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Thu, 16 Mar 2023 15:28:06 +0530 Subject: [PATCH] vc/intel/fsp/mtl: Add tCCD_L_WR to MemInfoHob as per FSP v3064 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch updates the Memory Hob Info data structure as per FSP v3064 source code change. BUG=b:273894357 TEST=Able to see `smbios type 17` table while booting google/rex. Without this patch: [DEBUG] 0 DIMM found With this patch: [DEBUG] 8 DIMM found Signed-off-by: Subrata Banik Change-Id: I3885fa7143cecc0b56e20278b69951c548ac451b Reviewed-on: https://review.coreboot.org/c/coreboot/+/73755 Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) Reviewed-by: Ronak Kanabar Reviewed-by: Eric Lai Reviewed-by: Kapil Porwal --- src/vendorcode/intel/fsp/fsp2_0/meteorlake/MemInfoHob.h | 1 + 1 file changed, 1 insertion(+) diff --git a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/MemInfoHob.h index 804644180d..e980f9ac56 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/MemInfoHob.h +++ b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/MemInfoHob.h @@ -192,6 +192,7 @@ typedef struct { UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups. UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups. UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group. + UINT16 tCCD_L_WR; ///< Number of tCK cycles for the channel DIMM's minimum Write-to-Write delay for same bank group. } MRC_CH_TIMING; typedef struct {