mb/google/kahlee: Add Grunt devicetree i2c bus cfg

I2C bus configuration is generally set up in devicetree.cb. This change
establishes listings for the buses so that they can be used (though
followup changes should update the buses to have correct timings).

BUG=b:72121803

Change-Id: I2b12c82d2bab42ab470aa207880be8876e7cb75f
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23407
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Justin TerAvest 2018-01-23 22:05:19 -07:00 committed by Aaron Durbin
parent 9d2ed4da66
commit 9a045cf203
1 changed files with 28 additions and 0 deletions

View File

@ -21,6 +21,34 @@ chip soc/amd/stoneyridge
register "uma_mode" = "UMAMODE_SPECIFIED_SIZE"
register "uma_size" = "128 * MiB"
# TODO(teravest): Fix speeds here.
register "i2c[0]" = "{
.speed = I2C_SPEED_FAST,
.rise_time_ns = 104,
.fall_time_ns = 52,
}"
# TODO(teravest): Fix speeds here.
register "i2c[1]" = "{
.speed = I2C_SPEED_FAST,
.rise_time_ns = 104,
.fall_time_ns = 52,
}"
# TODO(teravest): Fix speeds here.
register "i2c[2]" = "{
.speed = I2C_SPEED_FAST,
.rise_time_ns = 104,
.fall_time_ns = 52,
}"
# TODO(teravest): Fix speeds here.
register "i2c[3]" = "{
.speed = I2C_SPEED_FAST,
.rise_time_ns = 104,
.fall_time_ns = 52,
}"
device cpu_cluster 0 on
device lapic 10 on end
end