soc/intel/xeon_sp/skx: Simplify pci_domain_read_resource
Use a simpler pci_domain_read_resource for the stacks. This makes it the same as the cpx function, since both get the stack information from the FSP. This will be merged with common xeon cpx/skx in a later patch. Change-Id: I0130ce671fe9ff04e48021a0c5841551210aa827 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46308 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -405,44 +405,6 @@ static void assign_stack_resources(struct iiostack_resource *stack_list,
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}
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}
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static void xeonsp_constrain_pci_resources(struct device *dev, struct resource *res, void *data)
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{
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STACK_RES *stack = (STACK_RES *) data;
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if (!(res->flags & IORESOURCE_FIXED))
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return;
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uint64_t base, limit;
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if (res->flags & IORESOURCE_IO) {
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base = stack->PciResourceIoBase;
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limit = stack->PciResourceIoLimit;
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} else if ((res->flags & IORESOURCE_MEM) && (res->flags & IORESOURCE_PCI64)) {
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base = stack->PciResourceMem64Base;
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limit = stack->PciResourceMem64Limit;
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} else {
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base = stack->PciResourceMem32Base;
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limit = stack->PciResourceMem32Limit;
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}
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if (((res->base + res->size - 1) < base) || (res->base > limit)) /* outside window */
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return;
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if (res->limit > limit) /* resource end is out of limit */
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limit = res->base - 1;
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else
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base = res->base + res->size;
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if (res->flags & IORESOURCE_IO) {
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stack->PciResourceIoBase = base;
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stack->PciResourceIoLimit = limit;
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} else if ((res->flags & IORESOURCE_MEM) && (res->flags & IORESOURCE_PCI64)) {
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stack->PciResourceMem64Base = base;
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stack->PciResourceMem64Limit = limit;
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} else {
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stack->PciResourceMem32Base = base;
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stack->PciResourceMem32Limit = limit;
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}
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}
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static void xeonsp_pci_domain_read_resources(struct device *dev)
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{
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struct bus *link;
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@ -464,18 +426,21 @@ static void xeonsp_pci_domain_read_resources(struct device *dev)
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for (link = dev->link_list; link; link = link->next)
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xeonsp_pci_dev_iterator(link, xeonsp_reset_pci_op, NULL, NULL);
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/*
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* 1. group devices, resources for each stack
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* 2. order resources in descending order of requested resource allocation sizes
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*/
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struct iiostack_resource stack_info = {0};
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get_iiostack_info(&stack_info);
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/* constrain stack window */
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for (link = dev->link_list; link; link = link->next) {
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STACK_RES *stack = find_stack_for_bus(&stack_info, link->secondary);
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assert(stack != 0);
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xeonsp_pci_dev_iterator(link, NULL, xeonsp_constrain_pci_resources, stack);
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uint8_t pci64bit_alloc_flag = get_iiostack_info(&stack_info);
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if (!pci64bit_alloc_flag) {
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/*
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* Split 32 bit address space between prefetchable and
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* non-prefetchable windows
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*/
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for (int s = 0; s < stack_info.no_of_stacks; ++s) {
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STACK_RES *res = &stack_info.res[s];
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uint64_t length = (res->PciResourceMem32Limit -
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res->PciResourceMem32Base + 1)/2;
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res->PciResourceMem64Limit = res->PciResourceMem32Limit;
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res->PciResourceMem32Limit = (res->PciResourceMem32Base + length - 1);
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res->PciResourceMem64Base = res->PciResourceMem32Limit + 1;
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}
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}
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/* assign resources */
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