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mb/intel/adlrvp_n: Configure EC in RW GPIO 

EC_IN_RW signal from EC GPIO is connected to GPIO E7 of SOC. This GPIO
can be used to check EC status trusted (LOW: in RO) or untrusted (HIGH:
in RW).

BRANCH=None
BUG=None
TEST=Issue manual recovery and confirm DUT is entering recovery mode.

Change-Id: Ib8b6be9fcda24bd2bb479b5b6c01f24a6e9c7b1f
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60896
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
This commit is contained in:
Krishna Prasad Bhat 2022-01-07 16:39:53 +05:30 committed by Felix Held
parent 0fd734046a
commit 9a14fab340
2 changed files with 4 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/mainboard/intel/adlrvp/chromeos.c
View File

@ -16,7 +16,8 @@ void fill_lb_gpios(struct lb_gpios *gpios)
{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
{GPIO_EC_IN_RW, ACTIVE_HIGH, gpio_get(GPIO_EC_IN_RW), "EC in RW"},
};
if (CONFIG(BOARD_INTEL_ADLRVP_P_EXT_EC) || CONFIG(BOARD_INTEL_ADLRVP_M_EXT_EC))
if (CONFIG(BOARD_INTEL_ADLRVP_P_EXT_EC) || CONFIG(BOARD_INTEL_ADLRVP_M_EXT_EC) ||
CONFIG(BOARD_INTEL_ADLRVP_N_EXT_EC))
lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
else
lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios) - 1);
@ -50,7 +51,8 @@ void mainboard_chromeos_acpi_generate(void)
chromeos_acpi_gpio_generate(gpios, num);
}
#if (CONFIG(BOARD_INTEL_ADLRVP_P_EXT_EC) || CONFIG(BOARD_INTEL_ADLRVP_M_EXT_EC))
#if (CONFIG(BOARD_INTEL_ADLRVP_P_EXT_EC) || CONFIG(BOARD_INTEL_ADLRVP_M_EXT_EC) ||\
CONFIG(BOARD_INTEL_ADLRVP_N_EXT_EC))
int get_ec_is_trusted(void)
{
/* EC is trusted if not in RW. */

3
src/mainboard/intel/adlrvp/gpio_n.c
View File

@ -26,9 +26,6 @@ static const struct pad_config gpio_table[] = {
/* EC_SLP_S0_CS_N */
PAD_CFG_GPO(GPP_E4, 1, PLTRST),
/* GPPC_E7_EC_SMI_N */
PAD_CFG_GPI_SMI(GPP_E7, NONE, PLTRST, EDGE_SINGLE, INVERT),
/* H15 : DDPB_CTRLCLK ==> DDIB_HDMI_CTRLCLK */
PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
/* H17 : DDPB_CTRLDATA ==> DDIB_HDMI_CTRLDATA */