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mb/{sm/x11,razor,libretrend}/dt: Use comma separated list for arrays 

In order to improve the readability of the settings, use a comma
separated list to assign values to their indexes instead of repeating
the option name for each index.

Don't convert the settings for PCIe root ports as they will be moved
into the devicetree to their related root ports at some later point.

While on it, remove superfluous comments related to modified lines.

Change-Id: I27bac17098beb8b6cb3942e68a37da0095f0d0bd
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78602
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
This commit is contained in:
Felix Singer 2023-10-23 17:37:21 +02:00 committed by Felix Singer
parent d5008a2e82
commit 9a1b47e8a0
6 changed files with 137 additions and 171 deletions
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45
src/mainboard/libretrend/lt1000/devicetree.cb
View File

@ -34,12 +34,16 @@ chip soc/intel/skylake
# FSP Configuration # FSP Configuration
register "SataSalpSupport" = "0" register "SataSalpSupport" = "0"
register "SataPortsEnable[0]" = "1" register "SataPortsEnable" = "{
register "SataPortsEnable[1]" = "1" [0] = 1,
register "SataPortsEnable[2]" = "1" [1] = 1,
register "SataPortsDevSlp[0]" = "0" [2] = 1,
register "SataPortsDevSlp[1]" = "0" }"
register "SataPortsDevSlp[2]" = "0" register "SataPortsDevSlp" = "{
[0] = 0,
[1] = 0,
[2] = 0,
}"
register "SataSpeedLimit" = "2" register "SataSpeedLimit" = "2"
register "DspEnable" = "1" register "DspEnable" = "1"
register "IoBufferOwnership" = "0" register "IoBufferOwnership" = "0"
@ -129,20 +133,23 @@ chip soc/intel/skylake
register "PcieRpClkSrcNumber[10]" = "3" register "PcieRpClkSrcNumber[10]" = "3"
register "PcieRpClkSrcNumber[11]" = "3" register "PcieRpClkSrcNumber[11]" = "3"
register "usb2_ports" = "{
[0] = USB2_PORT_MID(OC_SKIP), /* Type-A Port (right) */
[1] = USB2_PORT_MID(OC_SKIP), /* Type-A Port (right) */
[2] = USB2_PORT_MID(OC_SKIP), /* WiFi */
[3] = USB2_PORT_MID(OC_SKIP), /* F_USB3 header */
[4] = USB2_PORT_MID(OC_SKIP), /* F_USB3 header */
[5] = USB2_PORT_MID(OC_SKIP), /* Type-A Port (left) */
[6] = USB2_PORT_MID(OC_SKIP), /* Type-A Port (left) */
[7] = USB2_PORT_MID(OC_SKIP), /* GL850G for F_USB1 and F_USB2 headers */
}"
register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port (right) register "usb3_ports" = "{
register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port (right) [0] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-A Port (right) */
register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # WiFi [1] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-A Port (right) */
register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # F_USB3 header [2] = USB3_PORT_DEFAULT(OC_SKIP), /* F_USB3 header */
register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # F_USB3 header [3] = USB3_PORT_DEFAULT(OC_SKIP), /* F_USB3 header */
register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port (left) }"
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port (left)
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # GL850G for F_USB1 and F_USB2 headers
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port (right)
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port (right)
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # F_USB3 header
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # F_USB3 header
# PL2 override 25W # PL2 override 25W
register "power_limits_config" = "{ register "power_limits_config" = "{

40
src/mainboard/razer/blade_stealth_kbl/devicetree.cb
View File

@ -23,9 +23,11 @@ chip soc/intel/skylake
# FSP Configuration # FSP Configuration
register "SataSalpSupport" = "0" register "SataSalpSupport" = "0"
register "SataPortsEnable[0]" = "0" register "SataPortsEnable" = "{
register "SataPortsEnable[1]" = "0" [0] = 0,
register "SataPortsEnable[2]" = "0" [1] = 0,
[2] = 0,
}"
register "DspEnable" = "0" register "DspEnable" = "0"
register "IoBufferOwnership" = "0" register "IoBufferOwnership" = "0"
register "SsicPortEnable" = "0" register "SsicPortEnable" = "0"
@ -124,23 +126,23 @@ chip soc/intel/skylake
register "PcieRpHotPlug[4]" = "1" register "PcieRpHotPlug[4]" = "1"
# USB register "usb2_ports" = "{
register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Type-A Port (right) [0] = USB2_PORT_MID(OC1), /* Type-A Port (right) */
register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # Type-A Port (left) [1] = USB2_PORT_MID(OC1), /* Type-A Port (left) */
[2] = USB2_PORT_MID(OC1), /* TODO Unknown. Maybe USBC? */
[3] = USB2_PORT_MID(OC1), /* TODO Unknown. Maybe USBC? */
[4] = USB2_PORT_MID(OC1), /* TODO Unknown. Maybe USBC? */
[5] = USB2_PORT_MID(OC1), /* TODO Unknown. Maybe USBC? */
[6] = USB2_PORT_FLEX(OC2), /* Camera */
[7] = USB2_PORT_FLEX(OC2), /* Keyboard */
[8] = USB2_PORT_FLEX(OC2), /* Touchscreen */
}"
register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" # TODO Unknown. Maybe USBC? register "usb3_ports" = "{
register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" # TODO Unknown. Maybe USBC? [0] = USB3_PORT_DEFAULT(OC1), /* Type-A Port (left) */
register "usb2_ports[4]" = "USB2_PORT_MID(OC1)" # TODO Unknown. Maybe USBC? [1] = USB3_PORT_DEFAULT(OC1), /* Type-A Port (right) */
register "usb2_ports[5]" = "USB2_PORT_MID(OC1)" # TODO Unknown. Maybe USBC? [5] = USB3_PORT_DEFAULT(OC1), /* TODO Unknown. Maybe USBC? */
}"
register "usb2_ports[6]" = "USB2_PORT_FLEX(OC2)" # Camera
register "usb2_ports[7]" = "USB2_PORT_FLEX(OC2)" # Keyboard
register "usb2_ports[8]" = "USB2_PORT_FLEX(OC2)" # Touchscreen
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (left)
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (right)
register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)" # TODO Unknown. Maybe USBC?
# PL1 override 25W # PL1 override 25W
# PL2 override 44W # PL2 override 44W

57
src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb
View File

@ -15,41 +15,30 @@ chip soc/intel/skylake
# This board has an IGD with no output. # This board has an IGD with no output.
register "PrimaryDisplay" = "Display_Auto" register "PrimaryDisplay" = "Display_Auto"
# USB configuration register "usb2_ports" = "{
# USB2/3 [0] = USB2_PORT_MID(OC0), /* USB 2 */
register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" [1] = USB2_PORT_MID(OC0), /* USB 3 */
register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" [2] = USB2_PORT_MID(OC1), /* USB 4 */
[3] = USB2_PORT_MID(OC1), /* USB 5 */
[4] = USB2_PORT_MID(OC2), /* USB 0 */
[5] = USB2_PORT_MID(OC2), /* USB 1 */
[8] = USB2_PORT_MID(OC3), /* USB 9 (3.0) */
[9] = USB2_PORT_MID(OC5), /* USB 8 (3.0) */
[10] = USB2_PORT_MID(OC4), /* USB 6 (3.0) */
[11] = USB2_PORT_MID(OC4), /* USB 7 (3.0) */
[12] = USB2_PORT_MID(OC3), /* USB 10 (3.0) */
[13] = USB2_PORT_MID(OC_SKIP), /* IPMI USB hub */
[14] = USB2_PORT_MID(OC0), /* Unknown */
[15] = USB2_PORT_MID(OC0), /* Unknown */
}"
# ? register "usb3_ports" = "{
register "usb2_ports[14]" = "USB2_PORT_MID(OC0)" [0] = USB3_PORT_DEFAULT(OC5), /* USB 8 */
register "usb2_ports[15]" = "USB2_PORT_MID(OC0)" [1] = USB3_PORT_DEFAULT(OC4), /* USB 6 */
[2] = USB3_PORT_DEFAULT(OC4), /* USB 7 */
# USB4/5 [3] = USB3_PORT_DEFAULT(OC3), /* USB 9 */
register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" [4] = USB3_PORT_DEFAULT(OC3), /* USB 10 */
register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" }"
# USB0/1
register "usb2_ports[4]" = "USB2_PORT_MID(OC2)"
register "usb2_ports[5]" = "USB2_PORT_MID(OC2)"
# USB9/10 (USB3.0)
register "usb2_ports[8]" = "USB2_PORT_MID(OC3)"
register "usb2_ports[12]" = "USB2_PORT_MID(OC3)"
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)"
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC3)"
# USB6/7 (USB3.0)
register "usb2_ports[10]" = "USB2_PORT_MID(OC4)"
register "usb2_ports[11]" = "USB2_PORT_MID(OC4)"
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC4)"
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC4)"
# USB8 (USB3.0)
register "usb2_ports[9]" = "USB2_PORT_MID(OC5)"
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC5)"
# IPMI USB HUB
register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)"
device domain 0 on device domain 0 on
device pci 01.0 on device pci 01.0 on

57
src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb
View File

@ -14,41 +14,30 @@ chip soc/intel/skylake
# FIXME: find out why FSP crashes without this # FIXME: find out why FSP crashes without this
register "PchHdaVcType" = "Vc1" register "PchHdaVcType" = "Vc1"
# USB configuration register "usb2_ports" = "{
# USB2/3 [0] = USB2_PORT_MID(OC0), /* USB 2 */
register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" [1] = USB2_PORT_MID(OC0), /* USB 3 */
register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" [2] = USB2_PORT_MID(OC1), /* USB 4 */
[3] = USB2_PORT_MID(OC1), /* USB 5 */
[4] = USB2_PORT_MID(OC2), /* USB 0 */
[5] = USB2_PORT_MID(OC2), /* USB 1 */
[8] = USB2_PORT_MID(OC3), /* USB 9 (3.0) */
[9] = USB2_PORT_MID(OC5), /* USB 8 (3.0) */
[10] = USB2_PORT_MID(OC4), /* USB 6 (3.0) */
[11] = USB2_PORT_MID(OC4), /* USB 7 (3.0) */
[12] = USB2_PORT_MID(OC3), /* USB 10 (3.0) */
[13] = USB2_PORT_MID(OC_SKIP), /* IPMI USB hub */
[14] = USB2_PORT_MID(OC0), /* Unknown */
[15] = USB2_PORT_MID(OC0), /* Unknown */
}"
# ? register "usb3_ports" = "{
register "usb2_ports[14]" = "USB2_PORT_MID(OC0)" [0] = USB3_PORT_DEFAULT(OC5), /* USB 8 */
register "usb2_ports[15]" = "USB2_PORT_MID(OC0)" [1] = USB3_PORT_DEFAULT(OC4), /* USB 6 */
[2] = USB3_PORT_DEFAULT(OC4), /* USB 7 */
# USB4/5 [3] = USB3_PORT_DEFAULT(OC3), /* USB 9 */
register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" [4] = USB3_PORT_DEFAULT(OC3), /* USB 10 */
register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" }"
# USB0/1
register "usb2_ports[4]" = "USB2_PORT_MID(OC2)"
register "usb2_ports[5]" = "USB2_PORT_MID(OC2)"
# USB9/10 (USB3.0)
register "usb2_ports[8]" = "USB2_PORT_MID(OC3)"
register "usb2_ports[12]" = "USB2_PORT_MID(OC3)"
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)"
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC3)"
# USB6/7 (USB3.0)
register "usb2_ports[10]" = "USB2_PORT_MID(OC4)"
register "usb2_ports[11]" = "USB2_PORT_MID(OC4)"
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC4)"
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC4)"
# USB8 (USB3.0)
register "usb2_ports[9]" = "USB2_PORT_MID(OC5)"
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC5)"
# IPMI USB HUB
register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)"
device domain 0 on device domain 0 on
device pci 01.0 on end # unused device pci 01.0 on end # unused

51
src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb
View File

@ -11,37 +11,28 @@ chip soc/intel/skylake
register "gen1_dec" = "0x007c0a01" # Super IO SWC register "gen1_dec" = "0x007c0a01" # Super IO SWC
register "gen2_dec" = "0x000c0ca1" # IPMI KCS register "gen2_dec" = "0x000c0ca1" # IPMI KCS
# USB configuration register "usb2_ports" = "{
# USB0/1 [0] = USB2_PORT_MID(OC3), /* USB 9 (3.0) */
register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" [1] = USB2_PORT_MID(OC3), /* USB 8 (3.0) */
register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" [2] = USB2_PORT_MID(OC1), /* USB 3 */
[3] = USB2_PORT_MID(OC1), /* USB 2 */
[4] = USB2_PORT_MID(OC2), /* USB 1 */
[5] = USB2_PORT_MID(OC2), /* USB 0 */
[6] = USB2_PORT_MID(OC0), /* USB 5 */
[7] = USB2_PORT_MID(OC0), /* USB 4 */
[8] = USB2_PORT_MID(OC_SKIP), /* IPMI USB HUB */
[9] = USB2_PORT_MID(OC5), /* USB 10 (3.0) */
[10] = USB2_PORT_MID(OC4), /* USB 7 (3.0) */
[11] = USB2_PORT_MID(OC4), /* USB 6 (3.0) */
}"
# USB2/3 register "usb3_ports" = "{
register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" [0] = USB3_PORT_DEFAULT(OC4), /* USB 7 */
register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" [1] = USB3_PORT_DEFAULT(OC4), /* USB 6 */
[2] = USB3_PORT_DEFAULT(OC5), /* USB 10 */
# USB4/5 [3] = USB3_PORT_DEFAULT(OC3), /* USB 9 */
register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" [4] = USB3_PORT_DEFAULT(OC3), /* USB 8 */
register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" }"
# USB6/7 (USB3.0)
register "usb2_ports[11]" = "USB2_PORT_MID(OC4)"
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC4)"
register "usb2_ports[10]" = "USB2_PORT_MID(OC4)"
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC4)"
# USB8/9 (USB3.0)
register "usb2_ports[1]" = "USB2_PORT_MID(OC3)"
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC3)"
register "usb2_ports[0]" = "USB2_PORT_MID(OC3)"
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)"
# USB10 (USB3.0)
register "usb2_ports[9]" = "USB2_PORT_MID(OC5)"
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC5)"
# IPMI USB HUB
register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)"
device domain 0 on device domain 0 on
subsystemid 0x15d9 0x0896 inherit subsystemid 0x15d9 0x0896 inherit

58
src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb
View File

@ -15,43 +15,31 @@ chip soc/intel/skylake
# This board has an IGD with no output. # This board has an IGD with no output.
register "PrimaryDisplay" = "Display_Auto" register "PrimaryDisplay" = "Display_Auto"
# USB configuration
# NB: Overcurrent OCx values untested # NB: Overcurrent OCx values untested
# USB2/3 register "usb2_ports" = "{
register "usb2_ports[8]" = "USB2_PORT_MID(OC0)" [0] = USB2_PORT_MID(OC3), /* USB 6 (3.0) */
register "usb2_ports[9]" = "USB2_PORT_MID(OC0)" [1] = USB2_PORT_MID(OC3), /* USB 7 (3.0) */
[2] = USB2_PORT_MID(OC2), /* USB 0 */
[3] = USB2_PORT_MID(OC2), /* USB 1 */
[4] = USB2_PORT_MID(OC1), /* USB 4 */
[5] = USB2_PORT_MID(OC1), /* USB 5 */
[8] = USB2_PORT_MID(OC0), /* USB 2 */
[9] = USB2_PORT_MID(OC0), /* USB 3 */
[10] = USB2_PORT_MID(OC5), /* USB 9 (3.0) */
[11] = USB2_PORT_MID(OC5), /* USB 10 (3.0) */
[12] = USB2_PORT_MID(OC4), /* USB 8 (3.0) */
[13] = USB2_PORT_MID(OC_SKIP), /* IPMI USB hub */
[14] = USB2_PORT_MID(OC0), /* Unknown */
[15] = USB2_PORT_MID(OC0), /* Unknown */
}"
# ? register "usb3_ports" = "{
register "usb2_ports[14]" = "USB2_PORT_MID(OC0)" [0] = USB3_PORT_DEFAULT(OC3), /* USB 6 */
register "usb2_ports[15]" = "USB2_PORT_MID(OC0)" [1] = USB3_PORT_DEFAULT(OC3), /* USB 7 */
[2] = USB3_PORT_DEFAULT(OC4), /* USB 8 */
# USB4/5 [3] = USB3_PORT_DEFAULT(OC5), /* USB 9 */
register "usb2_ports[4]" = "USB2_PORT_MID(OC1)" [4] = USB3_PORT_DEFAULT(OC5), /* USB 10 */
register "usb2_ports[5]" = "USB2_PORT_MID(OC1)" }"
# USB0/1
register "usb2_ports[2]" = "USB2_PORT_MID(OC2)"
register "usb2_ports[3]" = "USB2_PORT_MID(OC2)"
# USB6/7 (USB3.0)
register "usb2_ports[0]" = "USB2_PORT_MID(OC3)"
register "usb2_ports[1]" = "USB2_PORT_MID(OC3)"
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)"
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)"
# USB8 (USB3.0)
register "usb2_ports[12]" = "USB2_PORT_MID(OC4)"
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC4)"
# USB9/10 (USB3.0)
register "usb2_ports[10]" = "USB2_PORT_MID(OC5)"
register "usb2_ports[11]" = "USB2_PORT_MID(OC5)"
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC5)"
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC5)"
# IPMI USB HUB
register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)"
device domain 0 on device domain 0 on
device pci 01.0 on device pci 01.0 on