mb/amd/gardenia,pademelon: rewrite IRQ mapping handling
Gardenia and Pademelon had the same mainboard_picr_data and mainboard_intr_data data arrays. Compared to Kahlee there were 4 differences for PIRQ_F, PIRQ_SCI, PIRQ_SD and PIRQ_SATA in the IRQ data arrays. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia460b467990be7c3e6261440505988a9770ea084 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68852 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Held
parent
7e247a3fa8
commit
9a1da4bd07
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@ -3,65 +3,90 @@
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#include <device/device.h>
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#include <amdblocks/agesawrapper.h>
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#include <amdblocks/amd_pci_util.h>
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#include <console/console.h>
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#include <soc/gpio.h>
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#include <soc/southbridge.h>
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#include <string.h>
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#include "gpio.h"
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/***********************************************************
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/*
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* These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
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* This table is responsible for physically routing the PIC and
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* IOAPIC IRQs to the different PCI devices on the system. It
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* is read and written via registers 0xC00/0xC01 as an
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* Index/Data pair. These values are chipset and mainboard
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* dependent and should be updated accordingly.
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*
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* These values are used by the PCI configuration space,
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* MP Tables. TODO: Make ACPI use these values too.
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*/
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static const u8 mainboard_picr_data[FCH_IRQ_ROUTING_ENTRIES] = {
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[0x00] = 0x03, 0x04, 0x05, 0x07, 0x0B, 0x0A, 0x1F, 0x1F,
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[0x08] = 0xFA, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
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[0x10] = 0x1F, 0x1F, 0x1F, 0x03, 0x1F, 0x1F, 0x1F, 0x1F,
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[0x18] = 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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[0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00,
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[0x28] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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[0x30] = 0x05, 0x04, 0x05, 0x04, 0x04, 0x05, 0x04, 0x05,
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[0x38] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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[0x40] = 0x04, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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[0x48] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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[0x50] = 0x03, 0x04, 0x05, 0x07, 0x1F, 0x1F, 0x1F, 0x1F,
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[0x58] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
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[0x60] = 0x1F, 0x1F, 0x07, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
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[0x68] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
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[0x70] = 0x03, 0x0F, 0x06, 0x0E, 0x0A, 0x0B, 0x1F, 0x1F,
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[0x78] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
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static uint8_t fch_pic_routing[FCH_IRQ_ROUTING_ENTRIES];
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static uint8_t fch_apic_routing[FCH_IRQ_ROUTING_ENTRIES];
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static const struct fch_irq_routing fch_irq_map[] = {
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{ PIRQ_A, 3, 16 },
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{ PIRQ_B, 4, 17 },
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{ PIRQ_C, 5, 18 },
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{ PIRQ_D, 7, 19 },
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{ PIRQ_E, 11, 20 },
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{ PIRQ_F, 10, 21 },
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{ PIRQ_G, PIRQ_NC, 22 },
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{ PIRQ_H, PIRQ_NC, 23 },
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{ PIRQ_SCI, PIRQ_NC, 9 },
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{ PIRQ_SMBUS, PIRQ_NC, PIRQ_NC },
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{ PIRQ_HDA, 3, 16 },
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{ PIRQ_SD, PIRQ_NC, 16 },
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{ PIRQ_SDIO, PIRQ_NC, PIRQ_NC },
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{ PIRQ_EHCI, 5, 18 },
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{ PIRQ_XHCI, 4, 18 },
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{ PIRQ_SATA, PIRQ_NC, 19 },
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{ PIRQ_GPIO, 7, 7 },
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{ PIRQ_I2C0, 3, 3 },
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{ PIRQ_I2C1, 15, 15 },
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{ PIRQ_I2C2, 6, 6 },
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{ PIRQ_I2C3, 14, 14 },
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{ PIRQ_UART0, 10, 10 },
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{ PIRQ_UART1, 11, 11 },
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/* The MISC registers are not interrupt numbers */
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{ PIRQ_MISC, 0xfa, 0x00 },
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{ PIRQ_MISC0, 0xf1, 0x00 },
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{ PIRQ_MISC1, 0x00, 0x00 },
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{ PIRQ_MISC2, 0x00, 0x00 },
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};
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static const u8 mainboard_intr_data[FCH_IRQ_ROUTING_ENTRIES] = {
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[0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
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[0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
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[0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x1F, 0x1F, 0x10,
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[0x18] = 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00,
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[0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00,
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[0x28] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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[0x30] = 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00,
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[0x38] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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[0x40] = 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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[0x48] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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[0x50] = 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00,
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[0x58] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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[0x60] = 0x1F, 0x1F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00,
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[0x68] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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[0x70] = 0x03, 0x0F, 0x06, 0x0E, 0x0A, 0x0B, 0x1F, 0x1F,
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[0x78] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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};
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static const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length)
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{
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*length = ARRAY_SIZE(fch_irq_map);
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return fch_irq_map;
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}
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static void init_tables(void)
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{
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const struct fch_irq_routing *mb_irq_map;
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size_t mb_fch_irq_mapping_table_size;
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size_t i;
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mb_irq_map = mb_get_fch_irq_mapping(&mb_fch_irq_mapping_table_size);
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memset(fch_pic_routing, PIRQ_NC, sizeof(fch_pic_routing));
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memset(fch_apic_routing, PIRQ_NC, sizeof(fch_apic_routing));
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for (i = 0; i < mb_fch_irq_mapping_table_size; i++) {
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if (mb_irq_map[i].intr_index >= FCH_IRQ_ROUTING_ENTRIES) {
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printk(BIOS_WARNING,
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"Invalid IRQ index %u in FCH IRQ routing table entry %zu\n",
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mb_irq_map[i].intr_index, i);
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continue;
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}
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fch_pic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].pic_irq_num;
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fch_apic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].apic_irq_num;
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}
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}
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/* PIRQ Setup */
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static void pirq_setup(void)
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{
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intr_data_ptr = mainboard_intr_data;
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picr_data_ptr = mainboard_picr_data;
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intr_data_ptr = fch_apic_routing;
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picr_data_ptr = fch_pic_routing;
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}
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static void mainboard_init(void *chip_info)
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@ -77,6 +102,7 @@ static void mainboard_init(void *chip_info)
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*************************************************/
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static void mainboard_enable(struct device *dev)
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{
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init_tables();
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/* Initialize the PIRQ data structures for consumption */
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pirq_setup();
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}
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@ -3,60 +3,85 @@
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#include <device/device.h>
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#include <amdblocks/agesawrapper.h>
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#include <amdblocks/amd_pci_util.h>
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#include <console/console.h>
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#include <soc/gpio.h>
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#include <soc/pci_devs.h>
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#include <soc/southbridge.h>
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#include <string.h>
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#include "gpio.h"
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/***********************************************************
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/*
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* These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
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* This table is responsible for physically routing the PIC and
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* IOAPIC IRQs to the different PCI devices on the system. It
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* is read and written via registers 0xC00/0xC01 as an
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* Index/Data pair. These values are chipset and mainboard
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* dependent and should be updated accordingly.
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*
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* These values are used by the PCI configuration space,
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* MP Tables.
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*/
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static const u8 mainboard_picr_data[FCH_IRQ_ROUTING_ENTRIES] = {
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[0x00] = 0x03, 0x04, 0x05, 0x07, 0x0B, 0x0A, 0x1F, 0x1F,
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[0x08] = 0xFA, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
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[0x10] = 0x1F, 0x1F, 0x1F, 0x03, 0x1F, 0x1F, 0x1F, 0x1F,
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[0x18] = 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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[0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00,
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[0x28] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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[0x30] = 0x05, 0x04, 0x05, 0x04, 0x04, 0x05, 0x04, 0x05,
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[0x38] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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[0x40] = 0x04, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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[0x48] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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[0x50] = 0x03, 0x04, 0x05, 0x07, 0x1F, 0x1F, 0x1F, 0x1F,
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[0x58] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
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[0x60] = 0x1F, 0x1F, 0x07, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
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[0x68] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
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[0x70] = 0x03, 0x0F, 0x06, 0x0E, 0x0A, 0x0B, 0x1F, 0x1F,
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[0x78] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
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static uint8_t fch_pic_routing[FCH_IRQ_ROUTING_ENTRIES];
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static uint8_t fch_apic_routing[FCH_IRQ_ROUTING_ENTRIES];
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static const struct fch_irq_routing fch_irq_map[] = {
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{ PIRQ_A, 3, 16 },
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{ PIRQ_B, 4, 17 },
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{ PIRQ_C, 5, 18 },
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{ PIRQ_D, 7, 19 },
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{ PIRQ_E, 11, 20 },
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{ PIRQ_F, 10, 21 },
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{ PIRQ_G, PIRQ_NC, 22 },
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{ PIRQ_H, PIRQ_NC, 23 },
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{ PIRQ_SCI, PIRQ_NC, 9 },
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{ PIRQ_SMBUS, PIRQ_NC, PIRQ_NC },
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{ PIRQ_HDA, 3, 16 },
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{ PIRQ_SD, PIRQ_NC, 16 },
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{ PIRQ_SDIO, PIRQ_NC, PIRQ_NC },
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{ PIRQ_EHCI, 5, 18 },
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{ PIRQ_XHCI, 4, 18 },
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{ PIRQ_SATA, PIRQ_NC, 19 },
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{ PIRQ_GPIO, 7, 7 },
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{ PIRQ_I2C0, 3, 3 },
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{ PIRQ_I2C1, 15, 15 },
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{ PIRQ_I2C2, 6, 6 },
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{ PIRQ_I2C3, 14, 14 },
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{ PIRQ_UART0, 10, 10 },
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{ PIRQ_UART1, 11, 11 },
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/* The MISC registers are not interrupt numbers */
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{ PIRQ_MISC, 0xfa, 0x00 },
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{ PIRQ_MISC0, 0xf1, 0x00 },
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{ PIRQ_MISC1, 0x00, 0x00 },
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{ PIRQ_MISC2, 0x00, 0x00 },
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};
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static const u8 mainboard_intr_data[FCH_IRQ_ROUTING_ENTRIES] = {
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[0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
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[0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
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[0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x1F, 0x1F, 0x10,
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[0x18] = 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00,
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[0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00,
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[0x28] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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[0x30] = 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00,
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[0x38] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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[0x40] = 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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[0x48] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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[0x50] = 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00,
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[0x58] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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[0x60] = 0x1F, 0x1F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00,
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[0x68] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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[0x70] = 0x03, 0x0F, 0x06, 0x0E, 0x0A, 0x0B, 0x1F, 0x1F,
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[0x78] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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};
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static const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length)
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{
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*length = ARRAY_SIZE(fch_irq_map);
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return fch_irq_map;
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}
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static void init_tables(void)
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{
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const struct fch_irq_routing *mb_irq_map;
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size_t mb_fch_irq_mapping_table_size;
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size_t i;
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mb_irq_map = mb_get_fch_irq_mapping(&mb_fch_irq_mapping_table_size);
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memset(fch_pic_routing, PIRQ_NC, sizeof(fch_pic_routing));
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memset(fch_apic_routing, PIRQ_NC, sizeof(fch_apic_routing));
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for (i = 0; i < mb_fch_irq_mapping_table_size; i++) {
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if (mb_irq_map[i].intr_index >= FCH_IRQ_ROUTING_ENTRIES) {
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printk(BIOS_WARNING,
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"Invalid IRQ index %u in FCH IRQ routing table entry %zu\n",
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mb_irq_map[i].intr_index, i);
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continue;
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}
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fch_pic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].pic_irq_num;
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fch_apic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].apic_irq_num;
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}
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}
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/*
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* This table defines the index into the picr/intr_data tables for each
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@ -88,8 +113,8 @@ static void pirq_setup(void)
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{
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pirq_data_ptr = mainboard_pirq_data;
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pirq_data_size = ARRAY_SIZE(mainboard_pirq_data);
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intr_data_ptr = mainboard_intr_data;
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picr_data_ptr = mainboard_picr_data;
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intr_data_ptr = fch_apic_routing;
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picr_data_ptr = fch_pic_routing;
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}
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static void mainboard_init(void *chip_info)
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@ -105,6 +130,7 @@ static void mainboard_init(void *chip_info)
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*************************************************/
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static void mainboard_enable(struct device *dev)
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{
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init_tables();
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/* Initialize the PIRQ data structures for consumption */
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pirq_setup();
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}
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