From 9a24c3f80d477f304a966094ded1ccde4155375c Mon Sep 17 00:00:00 2001 From: Felix Held Date: Tue, 25 May 2021 20:45:08 +0200 Subject: [PATCH] soc/amd/cezanne: add devicetree setting for PSPP policy This allows boards to specify which PSPP policy (basically a dynamic trade-off between power consumption and PCIe link speed) should be used and also makes sure that the boards are using the expected PSPP policy and not just the UPD default from the FSP binary that has already changed once during the development. BUG=b:188793754 Signed-off-by: Felix Held Change-Id: I1b6459b2984711e72b79f5d4d90e04cb4b78d512 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54930 Reviewed-by: Matt Papageorge Reviewed-by: Raul Rangel Reviewed-by: Marshall Dawson Tested-by: build bot (Jenkins) --- src/soc/amd/cezanne/chip.h | 7 +++++++ src/soc/amd/cezanne/fsp_m_params.c | 3 +++ 2 files changed, 10 insertions(+) diff --git a/src/soc/amd/cezanne/chip.h b/src/soc/amd/cezanne/chip.h index 83aff05f18..df2059a260 100644 --- a/src/soc/amd/cezanne/chip.h +++ b/src/soc/amd/cezanne/chip.h @@ -94,6 +94,13 @@ struct soc_amd_cezanne_config { GPP_CLK_OFF, /* GPP clk off */ } gpp_clk_config[GPP_CLK_OUTPUT_COUNT]; + /* performance policy for the PCIe links: power consumption vs. link speed */ + enum { + DXIO_PSPP_PERFORMANCE = 0, + DXIO_PSPP_BALANCED, + DXIO_PSPP_POWERSAVE, + } pspp_policy; + uint8_t usb_phy_custom; struct usb_phy_config usb_phy; }; diff --git a/src/soc/amd/cezanne/fsp_m_params.c b/src/soc/amd/cezanne/fsp_m_params.c index 1e6f5ac26b..352aeef582 100644 --- a/src/soc/amd/cezanne/fsp_m_params.c +++ b/src/soc/amd/cezanne/fsp_m_params.c @@ -159,6 +159,9 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) mcfg->telemetry_vddcrsocOffset = config->telemetry_vddcrsocoffset; + /* PCIe power vs. speed */ + mcfg->pspp_policy = config->pspp_policy; + mcfg->enable_nb_azalia = devtree_gfx_hda_dev_enabled(); if (config->usb_phy_custom)