mb/google/myst: Enable eSPI SCI events
Enable EC SCI events for eSPI. BUG=b:275894894 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I8fd858c484f6fcf952bcb4f756ba2e4728091d8b Reviewed-on: https://review.coreboot.org/c/coreboot/+/74101 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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@ -1,9 +1,21 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <acpi/acpi.h>
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#include <amdblocks/smi.h>
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#include <ec/google/chromeec/ec.h>
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#include <gpio.h>
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#include <soc/smi.h>
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#include <variant/ec.h>
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static const struct sci_source espi_sci_sources[] = {
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{
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.scimap = SMITYPE_ESPI_SCI_B,
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.gpe = EC_SCI_GPI,
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.direction = SMI_SCI_LVL_HIGH, /* enum smi_sci_lvl */
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.level = SMI_SCI_EDG, /* enum smi_sci_dir */
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}
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};
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void mainboard_ec_init(void)
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{
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const struct google_chromeec_event_info info = {
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@ -15,4 +27,7 @@ void mainboard_ec_init(void)
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};
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google_chromeec_events_init(&info, acpi_is_wakeup_s3());
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/* Configure eSPI SCI events */
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gpe_configure_sci(espi_sci_sources, ARRAY_SIZE(espi_sci_sources));
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}
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@ -1,5 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <amdblocks/acpimmio.h>
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#include <amdblocks/amd_pci_util.h>
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#include <baseboard/variants.h>
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#include <console/console.h>
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@ -37,6 +38,10 @@ static void mainboard_init(void *chip_info)
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static void mainboard_enable(struct device *dev)
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{
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printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
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/* TODO: b/184678786 - Move into espi_config */
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/* Unmask eSPI IRQ 1 (Keyboard) */
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pm_write32(PM_ESPI_INTR_CTRL, PM_ESPI_DEV_INTR_MASK & ~(BIT(1)));
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}
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struct chip_operations mainboard_ops = {
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