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mb/google/skyrim/var/winterhold: Add Vrm setting for SMT 

All parameters of DPTC_INPUT() need to be configured on devicetree
when SOC_AMD_COMMON_BLOCK_ACPI_DPTC is enabled. The parameters without
configurations on devicetree would be 0 when
SOC_AMD_COMMON_BLOCK_ACPI_DPTC is enable. Follow AMD DevHub document
#57316. Configure vrm_current_limit_mA, vrm_maximum_current_limit_mA
and vrm_soc_current_limit_mA on devicetree with thermal table config E
as default table for SMT. Since the dynamic thermal table switching
mechanism is still under cooking, after discussing with thermal team,
suggest adopting config E(limit Soc not reach to max power) as default
thermal config to avoidany thermal-related issue during phase build.
Once the dynamic thermal table switching mechanism is finished, will
change the default value to config A.

BUG=b:258572474, b:248976976, b:259167917, b:257394883
TEST=emerge-skyrim coreboot

Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Change-Id: Ic1e7a46cac4119c7237d96a7bd0d23c8db028680
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
This commit is contained in:
EricKY Cheng 2022-11-19 01:50:57 +08:00 committed by Felix Held
parent 6a22c5f8ee
commit 9a41333c6b
1 changed files with 8 additions and 0 deletions
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8
src/mainboard/google/skyrim/variants/winterhold/overridetree.cb
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@ -26,6 +26,14 @@ chip soc/amd/mendocino
register "stt_error_coeff" = "0x21"
register "stt_error_rate_coefficient" = "0xCCD"
register "vrm_current_limit_mA" = "28000"
register "vrm_maximum_current_limit_mA" = "50000"
register "vrm_soc_current_limit_mA" = "10000"
# Throttle (e.g., Low/No Battery)
register "vrm_current_limit_throttle_mA" = "20000"
register "vrm_maximum_current_limit_throttle_mA" = "20000"
register "vrm_soc_current_limit_throttle_mA" = "10000"
device domain 0 on
device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A
device ref xhci_1 on # XHCI1 controller