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soc/intel/cnl: Select CSE defined ME spec version for cannonlake 

Cannonlake based SoCs uses Intel's Management Engine (ME), version 12.
This patch selects ME 12 specification defined at common code and
removes cannonlake SoC specific ME code and data structures.

BUG=b:260309647

Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: Ifc64cf63736bb730492b1732a22669a0415816a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73140
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Dinesh Gehlot 2023-02-20 13:57:16 +00:00 committed by Lean Sheng Tan
parent b17f9e6882
commit 9a5b743e56
4 changed files with 1 additions and 153 deletions
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1
src/soc/intel/cannonlake/Kconfig
View File

@ -97,6 +97,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
select SOC_INTEL_COMMON_BLOCK_HDA
select SOC_INTEL_COMMON_BLOCK_IRQ
select SOC_INTEL_COMMON_BLOCK_ME_SPEC_12
select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT
select SOC_INTEL_COMMON_BLOCK_SA
select SOC_INTEL_COMMON_BLOCK_SCS

1
src/soc/intel/cannonlake/Makefile.inc
View File

@ -37,7 +37,6 @@ ramstage-y += gspi.c
ramstage-y += i2c.c
ramstage-y += lockdown.c
ramstage-y += lpc.c
ramstage-y += me.c
ramstage-y += nhlt.c
ramstage-y += p2sb.c
ramstage-y += pmc.c

78
src/soc/intel/cannonlake/include/soc/me.h
View File

@ -1,78 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef _CANNONLAKE_ME_H_
#define _CANNONLAKE_ME_H_
/* ME Host Firmware Status register 1 */
union me_hfsts1 {
uint32_t data;
struct {
uint32_t working_state : 4;
uint32_t mfg_mode : 1;
uint32_t fpt_bad : 1;
uint32_t operation_state : 3;
uint32_t fw_init_complete : 1;
uint32_t ft_bup_ld_flr : 1;
uint32_t update_in_progress : 1;
uint32_t error_code : 4;
uint32_t operation_mode : 4;
uint32_t reserved_0 : 4;
uint32_t boot_options_present : 1;
uint32_t reserved_1 : 6;
uint32_t d0i3_support_valid : 1;
} __packed fields;
};
/* Host Firmware Status Register 2 */
union me_hfsts2 {
uint32_t data;
struct {
uint32_t reserved_0 : 4;
uint32_t cpu_replaced : 1;
uint32_t reserved_1 : 3;
uint32_t cpu_replaced_valid : 1;
uint32_t low_power_state : 1;
uint32_t reserved_2 : 22;
} __packed fields;
};
/* ME Host Firmware Status Register 3 */
union me_hfsts3 {
uint32_t data;
struct {
uint32_t reserved_0 : 4;
uint32_t fw_sku : 3;
uint32_t reserved_1 : 25;
} __packed fields;
};
/* Host Firmware Status Register 4 */
union me_hfsts4 {
uint32_t data;
struct {
uint32_t reserved_0;
} __packed fields;
};
/* Host Firmware Status Register 5 */
union me_hfsts5 {
uint32_t data;
struct {
uint32_t reserved_0;
} __packed fields;
};
/* Host Firmware Status Register 6 */
union me_hfsts6 {
uint32_t data;
struct {
uint32_t reserved_0 : 1;
uint32_t cpu_debug_disable : 1;
uint32_t reserved_1 : 29;
uint32_t txt_support : 1;
} __packed fields;
};
void dump_me_status(void *unused);
#endif /* _CANNONLAKE_ME_H_ */

74
src/soc/intel/cannonlake/me.c
View File

@ -1,74 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/pci_ops.h>
#include <bootstate.h>
#include <commonlib/helpers.h>
#include <console/console.h>
#include <device/pci.h>
#include <intelblocks/cse.h>
#include <soc/me.h>
#include <soc/pci_devs.h>
#include <stdint.h>
void dump_me_status(void *unused)
{
union me_hfsts1 hfsts1;
union me_hfsts2 hfsts2;
union me_hfsts3 hfsts3;
union me_hfsts4 hfsts4;
union me_hfsts5 hfsts5;
union me_hfsts6 hfsts6;
if (!is_cse_enabled())
return;
hfsts1.data = me_read_config32(PCI_ME_HFSTS1);
hfsts2.data = me_read_config32(PCI_ME_HFSTS2);
hfsts3.data = me_read_config32(PCI_ME_HFSTS3);
hfsts4.data = me_read_config32(PCI_ME_HFSTS4);
hfsts5.data = me_read_config32(PCI_ME_HFSTS5);
hfsts6.data = me_read_config32(PCI_ME_HFSTS6);
printk(BIOS_DEBUG, "ME: HFSTS1 : 0x%08X\n", hfsts1.data);
printk(BIOS_DEBUG, "ME: HFSTS2 : 0x%08X\n", hfsts2.data);
printk(BIOS_DEBUG, "ME: HFSTS3 : 0x%08X\n", hfsts3.data);
printk(BIOS_DEBUG, "ME: HFSTS4 : 0x%08X\n", hfsts4.data);
printk(BIOS_DEBUG, "ME: HFSTS5 : 0x%08X\n", hfsts5.data);
printk(BIOS_DEBUG, "ME: HFSTS6 : 0x%08X\n", hfsts6.data);
printk(BIOS_DEBUG, "ME: Manufacturing Mode : %s\n",
hfsts1.fields.mfg_mode ? "YES" : "NO");
printk(BIOS_DEBUG, "ME: FW Partition Table : %s\n",
hfsts1.fields.fpt_bad ? "BAD" : "OK");
printk(BIOS_DEBUG, "ME: Bringup Loader Failure : %s\n",
hfsts1.fields.ft_bup_ld_flr ? "YES" : "NO");
printk(BIOS_DEBUG, "ME: Firmware Init Complete : %s\n",
hfsts1.fields.fw_init_complete ? "YES" : "NO");
printk(BIOS_DEBUG, "ME: Boot Options Present : %s\n",
hfsts1.fields.boot_options_present ? "YES" : "NO");
printk(BIOS_DEBUG, "ME: Update In Progress : %s\n",
hfsts1.fields.update_in_progress ? "YES" : "NO");
printk(BIOS_DEBUG, "ME: D0i3 Support : %s\n",
hfsts1.fields.d0i3_support_valid ? "YES" : "NO");
printk(BIOS_DEBUG, "ME: Low Power State Enabled : %s\n",
hfsts2.fields.low_power_state ? "YES" : "NO");
printk(BIOS_DEBUG, "ME: CPU Replaced : %s\n",
hfsts2.fields.cpu_replaced ? "YES" : "NO");
printk(BIOS_DEBUG, "ME: CPU Replacement Valid : %s\n",
hfsts2.fields.cpu_replaced_valid ? "YES" : "NO");
printk(BIOS_DEBUG, "ME: Current Working State : %u\n",
hfsts1.fields.working_state);
printk(BIOS_DEBUG, "ME: Current Operation State : %u\n",
hfsts1.fields.operation_state);
printk(BIOS_DEBUG, "ME: Current Operation Mode : %u\n",
hfsts1.fields.operation_mode);
printk(BIOS_DEBUG, "ME: Error Code : %u\n",
hfsts1.fields.error_code);
printk(BIOS_DEBUG, "ME: CPU Debug Disabled : %s\n",
hfsts6.fields.cpu_debug_disable ? "YES" : "NO");
printk(BIOS_DEBUG, "ME: TXT Support : %s\n",
hfsts6.fields.txt_support ? "YES" : "NO");
}
BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, print_me_fw_version, NULL);
BOOT_STATE_INIT_ENTRY(BS_OS_RESUME_CHECK, BS_ON_EXIT, dump_me_status, NULL);