soc/mediatek/mt8186: Add RTC and clkbuf drivers
Add support for RTC and clkbuf. TEST=boot to kernel and check log ok BUG=b:202871018 Signed-off-by: Yuchen Huang <yuchen.huang@mediatek.corp-partner.google.com> Change-Id: Ia02a74f685feb2466c113a77cbfa3a7d8fedb595 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59344 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This commit is contained in:
Yuchen Huang
Hung-Te Lin
parent
c7e17bce06
commit
9a640c0f69
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@ -2,8 +2,10 @@
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#include <arch/stages.h>
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#include <soc/mt6366.h>
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#include <soc/rtc.h>
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void platform_romstage_main(void)
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{
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mt6366_init();
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rtc_boot();
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}
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@ -35,6 +35,7 @@ romstage-y += ../common/timer.c timer.c
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romstage-y += ../common/uart.c
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romstage-y += ../common/wdt.c wdt.c
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romstage-y += ../common/pmic_wrap.c pmic_wrap.c mt6366.c
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romstage-y += ../common/rtc.c ../common/rtc_osc_init.c rtc.c
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ramstage-y += ../common/auxadc.c
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ramstage-y += emi.c
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@ -54,6 +55,7 @@ ramstage-y += ../common/uart.c
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ramstage-y += ../common/usb.c usb.c
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ramstage-y += ../common/wdt.c wdt.c
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ramstage-y += ../common/pmic_wrap.c pmic_wrap.c mt6366.c
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ramstage-y += ../common/rtc.c ../common/rtc_osc_init.c rtc.c
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CPPFLAGS_common += -Isrc/soc/mediatek/mt8186/include
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CPPFLAGS_common += -Isrc/soc/mediatek/common/include
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@ -0,0 +1,240 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* This file is created based on MT8186 Functional Specification
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* Chapter number: 5.13
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*/
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#ifndef SOC_MEDIATEK_MT8186_RTC_H
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#define SOC_MEDIATEK_MT8186_RTC_H
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#include <soc/pmic_wrap_common.h>
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#include <soc/rtc_common.h>
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#include <stdbool.h>
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/* RTC registers */
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enum {
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RTC_BBPU = 0x0588,
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RTC_IRQ_STA = 0x058A,
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RTC_IRQ_EN = 0x058C,
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RTC_CII_EN = 0x058E,
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};
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enum {
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RTC_TC_SEC = 0x0592,
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RTC_TC_MIN = 0x0594,
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RTC_TC_HOU = 0x0596,
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RTC_TC_DOM = 0x0598,
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RTC_TC_DOW = 0x059A,
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RTC_TC_MTH = 0x059C,
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RTC_TC_YEA = 0x059E,
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};
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enum {
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RTC_AL_SEC = 0x05A0,
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RTC_AL_MIN = 0x05A2,
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RTC_AL_HOU = 0x05A4,
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RTC_AL_DOM = 0x05A6,
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RTC_AL_DOW = 0x05A8,
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RTC_AL_MTH = 0x05AA,
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RTC_AL_YEA = 0x05AC,
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RTC_AL_MASK = 0x0590,
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};
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enum {
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RTC_OSC32CON = 0x05AE,
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RTC_CON = 0x05C4,
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RTC_WRTGR = 0x05C2,
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};
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enum {
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RTC_POWERKEY1 = 0x05B0,
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RTC_POWERKEY2 = 0x05B2,
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};
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enum {
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RTC_PDN1 = 0x05B4,
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RTC_PDN2 = 0x05B6,
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RTC_SPAR0 = 0x05B8,
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RTC_SPAR1 = 0x05BA,
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RTC_PROT = 0x05BC,
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RTC_DIFF = 0x05BE,
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RTC_CALI = 0x05C0,
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};
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enum {
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RTC_BBPU_PWREN = 1U << 0,
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RTC_BBPU_CLR = 1U << 1,
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RTC_BBPU_INIT = 1U << 2,
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RTC_BBPU_AUTO = 1U << 3,
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RTC_BBPU_CLRPKY = 1U << 4,
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RTC_BBPU_RELOAD = 1U << 5,
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RTC_BBPU_CBUSY = 1U << 6,
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RTC_CBUSY_TIMEOUT_US = 8000,
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};
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enum {
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RTC_CON_VBAT_LPSTA_RAW = 1U << 0,
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RTC_CON_EOSC32_LPEN = 1U << 1,
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RTC_CON_XOSC32_LPEN = 1U << 2,
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RTC_CON_LPRST = 1U << 3,
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RTC_CON_CDBO = 1U << 4,
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RTC_CON_F32KOB = 1U << 5,
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RTC_CON_GPO = 1U << 6,
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RTC_CON_GOE = 1U << 7,
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RTC_CON_GSR = 1U << 8,
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RTC_CON_GSMT = 1U << 9,
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RTC_CON_GPEN = 1U << 10,
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RTC_CON_GPU = 1U << 11,
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RTC_CON_GE4 = 1U << 12,
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RTC_CON_GE8 = 1U << 13,
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RTC_CON_GPI = 1U << 14,
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RTC_CON_LPSTA_RAW = 1U << 15,
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};
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enum {
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RTC_XOSCCALI_MASK = 0x1F << 0,
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RTC_XOSC32_ENB = 1U << 5,
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RTC_EMB_HW_MODE = 0U << 6,
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RTC_EMB_K_EOSC32_MODE = 1U << 6,
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RTC_EMB_SW_DCXO_MODE = 2U << 6,
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RTC_EMB_SW_EOSC32_MODE = 3U << 6,
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RTC_EMBCK_SEL_MODE_MASK = 3U << 6,
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RTC_EMBCK_SRC_SEL = 1U << 8,
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RTC_EMBCK_SEL_OPTION = 1U << 9,
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RTC_GPS_CKOUT_EN = 1U << 10,
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RTC_REG_XOSC32_ENB = 1U << 15,
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};
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enum {
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RTC_LPD_OPT_XOSC_AND_EOSC_LPD = 0U << 13,
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RTC_LPD_OPT_EOSC_LPD = 1U << 13,
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RTC_LPD_OPT_XOSC_LPD = 2U << 13,
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RTC_LPD_OPT_F32K_CK_ALIVE = 3U << 13,
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RTC_LPD_OPT_MASK = 3U << 13,
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};
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/* PMIC TOP Register Definition */
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enum {
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PMIC_RG_SCK_TOP_CON0 = 0x050C,
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};
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/* PMIC TOP Register Definition */
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enum {
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PMIC_RG_TOP_CKPDN_CON0 = 0x010C,
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PMIC_RG_TOP_CKPDN_CON0_SET = 0x010E,
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PMIC_RG_TOP_CKPDN_CON0_CLR = 0x0110,
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PMIC_RG_TOP_CKPDN_CON1 = 0x0112,
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PMIC_RG_TOP_CKPDN_CON1_SET = 0x0114,
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PMIC_RG_TOP_CKPDN_CON1_CLR = 0x0116,
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PMIC_RG_TOP_CKSEL_CON0 = 0x0118,
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PMIC_RG_TOP_CKSEL_CON0_SET = 0x011A,
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PMIC_RG_TOP_CKSEL_CON0_CLR = 0x011C,
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};
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enum {
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PMIC_RG_FQMTR_32K_CK_PDN_SHIFT = 10,
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PMIC_RG_FQMTR_CK_PDN_SHIFT = 11,
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};
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/* PMIC DCXO Register Definition */
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enum {
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PMIC_RG_DCXO_CW00 = 0x0788,
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PMIC_RG_DCXO_CW00_CLR = 0x078C,
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PMIC_RG_DCXO_CW02 = 0x0790,
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PMIC_RG_DCXO_CW07 = 0x079A,
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PMIC_RG_DCXO_CW09 = 0x079E,
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PMIC_RG_DCXO_CW11 = 0x07A2,
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PMIC_RG_DCXO_CW13 = 0x07AA,
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PMIC_RG_DCXO_CW15 = 0x07AE,
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PMIC_RG_DCXO_CW16 = 0x07B0,
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PMIC_RG_DCXO_CW21 = 0x07BA,
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PMIC_RG_DCXO_CW23 = 0x07BE,
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PMIC_RG_DCXO_ELR0 = 0x07C4,
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};
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enum {
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PMIC_RG_TOP_TMA_KEY = 0x03A8,
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};
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/* PMIC Frequency Meter Definition */
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enum {
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PMIC_RG_FQMTR_CKSEL = 0x0118,
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PMIC_RG_FQMTR_RST = 0x013E,
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PMIC_RG_FQMTR_CON0 = 0x0514,
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PMIC_RG_FQMTR_WINSET = 0x0516,
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PMIC_RG_FQMTR_DATA = 0x0518,
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FQMTR_TIMEOUT_US = 8000,
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};
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enum {
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PMIC_FQMTR_FIX_CLK_26M = 0U << 0,
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PMIC_FQMTR_FIX_CLK_XOSC_32K_DET = 1U << 0,
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PMIC_FQMTR_FIX_CLK_EOSC_32K = 2U << 0,
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PMIC_FQMTR_FIX_CLK_RTC_32K = 3U << 0,
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PMIC_FQMTR_FIX_CLK_SMPS_CK = 4U << 0,
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PMIC_FQMTR_FIX_CLK_TCK_SEC = 5U << 0,
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PMIC_FQMTR_FIX_CLK_PMU_75K = 6U << 0,
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PMIC_FQMTR_CKSEL_MASK = 7U << 0,
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};
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enum {
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PMIC_FQMTR_RST_SHIFT = 8
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};
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enum {
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PMIC_FQMTR_CON0_XOSC32_CK = 0U << 0,
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PMIC_FQMTR_CON0_DCXO_F32K_CK = 1U << 0,
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PMIC_FQMTR_CON0_EOSC32_CK = 2U << 0,
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PMIC_FQMTR_CON0_XOSC32_CK_DETECTON = 3U << 0,
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PMIC_FQMTR_CON0_FQM26M_CK = 4U << 0,
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PMIC_FQMTR_CON0_FQM32k_CK = 5U << 0,
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PMIC_FQMTR_CON0_TEST_CK = 6U << 0,
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PMIC_FQMTR_CON0_TCKSEL_MASK = 7U << 0,
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PMIC_FQMTR_CON0_BUSY = 1U << 3,
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PMIC_FQMTR_CON0_DCXO26M_EN = 1U << 4,
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PMIC_FQMTR_CON0_FQMTR_EN = 1U << 15,
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};
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enum {
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RTC_FQMTR_LOW_BASE = 794 - 2,
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RTC_FQMTR_HIGH_BASE = 794 + 2,
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};
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enum {
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RTC_XOSCCALI_START = 0x00,
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RTC_XOSCCALI_END = 0x1f,
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};
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/* external API */
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void rtc_bbpu_power_on(void);
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int rtc_init(int recover);
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bool rtc_gpio_init(void);
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void rtc_boot(void);
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u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size);
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static inline s32 rtc_read(u16 addr, u16 *rdata)
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{
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s32 ret;
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ret = pwrap_read(addr, rdata);
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if (ret)
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rtc_info("pwrap_read failed: ret=%d\n", ret);
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return ret;
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}
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static inline s32 rtc_write(u16 addr, u16 wdata)
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{
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s32 ret;
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ret = pwrap_write(addr, wdata);
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if (ret)
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rtc_info("pwrap_write failed: ret=%d\n", ret);
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return ret;
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}
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#endif /* SOC_MEDIATEK_MT8186_RTC_H */
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@ -0,0 +1,361 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* This file is created based on MT8186 Functional Specification
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* Chapter number: 5.13
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*/
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#include <delay.h>
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#include <halt.h>
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#include <soc/rtc.h>
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#include <soc/rtc_common.h>
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#include <soc/mt6366.h>
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#include <soc/pmic_wrap.h>
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#include <timer.h>
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#define RTC_GPIO_USER_MASK ((1 << 13) - (1 << 8))
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/* Initialize RTC setting of using DCXO clock */
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static bool rtc_enable_dcxo(void)
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{
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u16 bbpu, con, osc32con, sec;
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rtc_read(RTC_BBPU, &bbpu);
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rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD);
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if (!rtc_write_trigger()) {
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rtc_info("rtc_write_trigger() failed\n");
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return false;
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}
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mdelay(1);
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if (!rtc_writeif_unlock()) {
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rtc_info("rtc_writeif_unlock() failed\n");
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return false;
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}
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rtc_read(RTC_OSC32CON, &osc32con);
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osc32con &= ~(RTC_EMBCK_SRC_SEL | RTC_EMBCK_SEL_MODE_MASK
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| RTC_GPS_CKOUT_EN);
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osc32con |= RTC_XOSC32_ENB | RTC_REG_XOSC32_ENB
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| RTC_EMB_K_EOSC32_MODE | RTC_EMBCK_SEL_OPTION;
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if (!rtc_xosc_write(osc32con)) {
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rtc_info("rtc_xosc_write() failed\n");
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return false;
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}
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rtc_read(RTC_CON, &con);
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rtc_read(RTC_OSC32CON, &osc32con);
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rtc_read(RTC_AL_SEC, &sec);
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rtc_info("con = %#x, osc32con = %#x, sec = %#x\n", con, osc32con, sec);
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return true;
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}
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/* Initialize RTC related gpio */
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bool rtc_gpio_init(void)
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{
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u16 con;
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/* RTC_32K1V8 clock change from 128k div 4 source to RTC 32k source */
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pwrap_write_field(PMIC_RG_TOP_CKSEL_CON0_SET, 0x1, 0x1, 3);
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/* Export 32K clock RTC_32K1V8_1 */
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pwrap_write_field(PMIC_RG_TOP_CKPDN_CON1_CLR, 0x1, 0x1, 1);
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/* Export 32K clock RTC_32K2V8 */
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rtc_read(RTC_CON, &con);
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con &= (RTC_CON_LPSTA_RAW | RTC_CON_LPRST | RTC_CON_EOSC32_LPEN
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| RTC_CON_XOSC32_LPEN);
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con |= (RTC_CON_GPEN | RTC_CON_GOE);
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con &= ~RTC_CON_F32KOB;
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rtc_write(RTC_CON, con);
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return rtc_write_trigger();
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}
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u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size)
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{
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u16 bbpu, osc32con;
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u16 fqmtr_busy, fqmtr_data, fqmtr_rst, fqmtr_tcksel;
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struct stopwatch sw;
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rtc_read(RTC_BBPU, &bbpu);
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rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD);
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if (!rtc_write_trigger()) {
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rtc_info("rtc_write_trigger() failed\n");
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return false;
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}
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rtc_read(RTC_OSC32CON, &osc32con);
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if (rtc_xosc_write((osc32con & ~RTC_XOSCCALI_MASK) |
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(val & RTC_XOSCCALI_MASK))) {
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rtc_info("rtc_xosc_write() failed\n");
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return false;
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}
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/* Enable FQMTR clock */
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pwrap_write_field(PMIC_RG_TOP_CKPDN_CON0_CLR, 1, 1,
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PMIC_RG_FQMTR_32K_CK_PDN_SHIFT);
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pwrap_write_field(PMIC_RG_TOP_CKPDN_CON0_CLR, 1, 1,
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PMIC_RG_FQMTR_CK_PDN_SHIFT);
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/* FQMTR reset */
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pwrap_write_field(PMIC_RG_FQMTR_RST, 1, 1, PMIC_FQMTR_RST_SHIFT);
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do {
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rtc_read(PMIC_RG_FQMTR_DATA, &fqmtr_data);
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rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_busy);
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} while (fqmtr_data && (fqmtr_busy & PMIC_FQMTR_CON0_BUSY));
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rtc_read(PMIC_RG_FQMTR_RST, &fqmtr_rst);
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/* FQMTR normal */
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pwrap_write_field(PMIC_RG_FQMTR_RST, 0, 1, PMIC_FQMTR_RST_SHIFT);
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/* Set frequency meter window value (0=1X32K(fixed clock)) */
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rtc_write(PMIC_RG_FQMTR_WINSET, window_size);
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/* Enable 26M and set test clock source */
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rtc_write(PMIC_RG_FQMTR_CON0, PMIC_FQMTR_CON0_DCXO26M_EN | measure_src);
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/* Enable 26M -> delay 100us -> enable FQMTR */
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udelay(100);
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rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_tcksel);
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/* Enable FQMTR */
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rtc_write(PMIC_RG_FQMTR_CON0, fqmtr_tcksel | PMIC_FQMTR_CON0_FQMTR_EN);
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udelay(100);
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stopwatch_init_usecs_expire(&sw, FQMTR_TIMEOUT_US);
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/* FQMTR read until ready */
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if (!wait_us(FQMTR_TIMEOUT_US,
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rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_busy) == 0 &&
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!(fqmtr_busy & PMIC_FQMTR_CON0_BUSY))) {
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rtc_info("get frequency time out: %#x\n", fqmtr_busy);
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return false;
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}
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/* Read data should be closed to 26M/32k = 794 */
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rtc_read(PMIC_RG_FQMTR_DATA, &fqmtr_data);
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|
||||
rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_tcksel);
|
||||
/* Disable FQMTR */
|
||||
rtc_write(PMIC_RG_FQMTR_CON0, fqmtr_tcksel & ~PMIC_FQMTR_CON0_FQMTR_EN);
|
||||
/* Disable FQMTR -> delay 100us -> disable 26M */
|
||||
udelay(100);
|
||||
/* Disable 26M */
|
||||
rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_tcksel);
|
||||
rtc_write(PMIC_RG_FQMTR_CON0,
|
||||
fqmtr_tcksel & ~PMIC_FQMTR_CON0_DCXO26M_EN);
|
||||
rtc_info("input = %#x, output = %#x\n", val, fqmtr_data);
|
||||
|
||||
/* Disable FQMTR clock */
|
||||
pwrap_write_field(PMIC_RG_TOP_CKPDN_CON0_SET, 1, 1,
|
||||
PMIC_RG_FQMTR_32K_CK_PDN_SHIFT);
|
||||
pwrap_write_field(PMIC_RG_TOP_CKPDN_CON0_SET, 1, 1,
|
||||
PMIC_RG_FQMTR_CK_PDN_SHIFT);
|
||||
|
||||
return fqmtr_data;
|
||||
}
|
||||
|
||||
/* Low power detect setting */
|
||||
static bool rtc_lpd_init(void)
|
||||
{
|
||||
u16 con, sec;
|
||||
|
||||
/* Set RTC_LPD_OPT */
|
||||
rtc_read(RTC_AL_SEC, &sec);
|
||||
sec |= RTC_LPD_OPT_F32K_CK_ALIVE;
|
||||
rtc_write(RTC_AL_SEC, sec);
|
||||
if (!rtc_write_trigger()) {
|
||||
rtc_info("rtc_write_trigger() failed\n");
|
||||
return false;
|
||||
}
|
||||
|
||||
/* Initialize XOSC32 to detect 32k clock stop */
|
||||
rtc_read(RTC_CON, &con);
|
||||
con |= RTC_CON_XOSC32_LPEN;
|
||||
if (!rtc_lpen(con))
|
||||
return false;
|
||||
|
||||
/* Initialize EOSC32 to detect RTC low power */
|
||||
rtc_read(RTC_CON, &con);
|
||||
con |= RTC_CON_EOSC32_LPEN;
|
||||
if (!rtc_lpen(con))
|
||||
return false;
|
||||
|
||||
rtc_read(RTC_CON, &con);
|
||||
con &= ~RTC_CON_XOSC32_LPEN;
|
||||
rtc_write(RTC_CON, con);
|
||||
|
||||
/* Set RTC_LPD_OPT */
|
||||
rtc_read(RTC_AL_SEC, &sec);
|
||||
sec &= ~RTC_LPD_OPT_MASK;
|
||||
sec |= RTC_LPD_OPT_EOSC_LPD;
|
||||
rtc_write(RTC_AL_SEC, sec);
|
||||
if (!rtc_write_trigger()) {
|
||||
rtc_info("rtc_write_trigger() failed\n");
|
||||
return false;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool rtc_hw_init(void)
|
||||
{
|
||||
u16 bbpu;
|
||||
|
||||
rtc_read(RTC_BBPU, &bbpu);
|
||||
rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_INIT);
|
||||
if (!rtc_write_trigger()) {
|
||||
rtc_info("rtc_write_trigger() failed\n");
|
||||
return false;
|
||||
}
|
||||
|
||||
udelay(500);
|
||||
|
||||
rtc_read(RTC_BBPU, &bbpu);
|
||||
rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD);
|
||||
if (!rtc_write_trigger()) {
|
||||
rtc_info("rtc_write_trigger() failed\n");
|
||||
return false;
|
||||
}
|
||||
|
||||
rtc_read(RTC_BBPU, &bbpu);
|
||||
if (bbpu & RTC_BBPU_INIT) {
|
||||
rtc_info("timeout\n");
|
||||
return false;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static void mt6366_dcxo_disable_unused(void)
|
||||
{
|
||||
/* Disable clock buffer XO_CEL */
|
||||
rtc_write(PMIC_RG_DCXO_CW00_CLR, 0x0800);
|
||||
/* Mask bblpm request and switch off bblpm mode */
|
||||
rtc_write(PMIC_RG_DCXO_CW23, 0x0052);
|
||||
}
|
||||
|
||||
/* Check RTC Initialization */
|
||||
int rtc_init(int recover)
|
||||
{
|
||||
int ret;
|
||||
|
||||
rtc_info("recovery: %d\n", recover);
|
||||
|
||||
/* Write powerkeys to enable RTC functions */
|
||||
if (!rtc_powerkey_init()) {
|
||||
ret = -RTC_STATUS_POWERKEY_INIT_FAIL;
|
||||
goto err;
|
||||
}
|
||||
|
||||
/* Write interface unlock need to be set after powerkey match */
|
||||
if (!rtc_writeif_unlock()) {
|
||||
ret = -RTC_STATUS_WRITEIF_UNLOCK_FAIL;
|
||||
goto err;
|
||||
}
|
||||
|
||||
rtc_osc_init();
|
||||
|
||||
/* In recovery mode, we need 20ms delay for register setting. */
|
||||
if (recover)
|
||||
mdelay(20);
|
||||
|
||||
if (!rtc_gpio_init()) {
|
||||
ret = -RTC_STATUS_GPIO_INIT_FAIL;
|
||||
goto err;
|
||||
}
|
||||
|
||||
if (!rtc_hw_init()) {
|
||||
ret = -RTC_STATUS_HW_INIT_FAIL;
|
||||
goto err;
|
||||
}
|
||||
|
||||
if (!rtc_reg_init()) {
|
||||
ret = -RTC_STATUS_REG_INIT_FAIL;
|
||||
goto err;
|
||||
}
|
||||
|
||||
if (!rtc_lpd_init()) {
|
||||
ret = -RTC_STATUS_LPD_INIT_FAIL;
|
||||
goto err;
|
||||
}
|
||||
|
||||
/*
|
||||
* After lpd init, powerkeys need to be written again to enable
|
||||
* low power detect function.
|
||||
*/
|
||||
if (!rtc_powerkey_init()) {
|
||||
ret = -RTC_STATUS_POWERKEY_INIT_FAIL;
|
||||
goto err;
|
||||
}
|
||||
|
||||
return RTC_STATUS_OK;
|
||||
err:
|
||||
rtc_info("init failed: ret = %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Enable RTC bbpu */
|
||||
void rtc_bbpu_power_on(void)
|
||||
{
|
||||
u16 bbpu;
|
||||
int ret;
|
||||
|
||||
/* Pull powerhold high, control by pmic */
|
||||
mt6366_set_power_hold(true);
|
||||
|
||||
/* Pull PWRBB high */
|
||||
bbpu = RTC_BBPU_KEY | RTC_BBPU_AUTO | RTC_BBPU_RELOAD | RTC_BBPU_PWREN;
|
||||
rtc_write(RTC_BBPU, bbpu);
|
||||
ret = rtc_write_trigger();
|
||||
rtc_info("rtc_write_trigger = %d\n", ret);
|
||||
|
||||
rtc_read(RTC_BBPU, &bbpu);
|
||||
rtc_info("done BBPU = %#x\n", bbpu);
|
||||
}
|
||||
|
||||
static void dcxo_init(void)
|
||||
{
|
||||
/* Buffer setting */
|
||||
rtc_write(PMIC_RG_DCXO_CW15, 0xA2AA);
|
||||
rtc_write(PMIC_RG_DCXO_CW13, 0x98E9);
|
||||
rtc_write(PMIC_RG_DCXO_CW16, 0x9855);
|
||||
|
||||
/* 26M enable control */
|
||||
/* Enable clock buffer XO_SOC, XO_CEL */
|
||||
rtc_write(PMIC_RG_DCXO_CW00, 0x4805);
|
||||
rtc_write(PMIC_RG_DCXO_CW11, 0x8000);
|
||||
|
||||
/* Load thermal coefficient */
|
||||
rtc_write(PMIC_RG_TOP_TMA_KEY, 0x9CA7);
|
||||
rtc_write(PMIC_RG_DCXO_CW21, 0x12A7);
|
||||
rtc_write(PMIC_RG_DCXO_ELR0, 0xD004);
|
||||
rtc_write(PMIC_RG_TOP_TMA_KEY, 0x0000);
|
||||
|
||||
/* Adjust OSC FPM setting */
|
||||
rtc_write(PMIC_RG_DCXO_CW07, 0x8FFE);
|
||||
|
||||
/* Re-calibrate OSC current */
|
||||
rtc_write(PMIC_RG_DCXO_CW09, 0x008F);
|
||||
udelay(100);
|
||||
rtc_write(PMIC_RG_DCXO_CW09, 0x408F);
|
||||
mdelay(5);
|
||||
|
||||
mt6366_dcxo_disable_unused();
|
||||
}
|
||||
|
||||
/* Initialize rtc boot flow */
|
||||
void rtc_boot(void)
|
||||
{
|
||||
/* DCXO clock initialized settings */
|
||||
dcxo_init();
|
||||
|
||||
/* DCXO 32k initialized settings */
|
||||
pwrap_write_field(PMIC_RG_DCXO_CW02, 0xF, 0xF, 0);
|
||||
pwrap_write_field(PMIC_RG_SCK_TOP_CON0, 0x1, 0x1, 0);
|
||||
|
||||
/* Use DCXO 32K clock */
|
||||
if (!rtc_enable_dcxo())
|
||||
rtc_info("rtc_enable_dcxo() failed\n");
|
||||
|
||||
rtc_boot_common();
|
||||
rtc_bbpu_power_on();
|
||||
}
|
||||
Loading…
Reference in New Issue