Cosmetics, whitespace, coding style, partially ident-aided (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3318 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Uwe Hermann
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.TH INTELTOOL 8 "May 12, 2008"
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.TH INTELTOOL 8 "May 14, 2008"
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.SH NAME
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inteltool \- a tool for dumping Intel(R) CPU / chipset configuration parameters
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.SH SYNOPSIS
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@ -7,9 +7,9 @@ inteltool \- a tool for dumping Intel(R) CPU / chipset configuration parameters
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.B inteltool
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is a handy little tool for dumping the configuration space of Intel(R)
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CPUs, northbridges and southbridges.
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.sp
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This tool has been developed for the coreboot project (see
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.B http://www.coreboot.org/
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.B http://coreboot.org
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for details on coreboot).
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.SH OPTIONS
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.TP
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@ -20,31 +20,32 @@ Show a help text and exit.
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Show version information and exit.
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.TP
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.B "\-a, \-\-all"
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Dump all known I/O Controller Hub (ICH) southbridge, Intel(R) northbridge and Intel(R) Core CPU MSRs.
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Dump all known I/O Controller Hub (ICH) southbridge, Intel(R) northbridge
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and Intel(R) Core CPU MSRs.
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.TP
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.B "\-g, \-\-gpio"
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Dump I/O Controller Hub (ICH) southbridge GPIO registers
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Dump I/O Controller Hub (ICH) southbridge GPIO registers.
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.TP
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.B "\-r, \-\-rcba"
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Dump I/O Controller Hub (ICH) southbridge RCBA registers
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Dump I/O Controller Hub (ICH) southbridge RCBA registers.
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.TP
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.B "\-p, \-\-pmbase"
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Dump I/O Controller Hub (ICH) southbridge pmbase registers
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Dump I/O Controller Hub (ICH) southbridge PMBASE registers.
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.TP
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.B "\-m, \-\-mchbar"
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Dump Intel(R) northbridge MCHBAR registers
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Dump Intel(R) northbridge MCHBAR registers.
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.TP
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.B "\-e, \-\-epbar"
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Dump Intel(R) northbridge EPBAR registers
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Dump Intel(R) northbridge EPBAR registers.
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.TP
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.B "\-d, \-\-dmibar"
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Dump Intel(R) northbridge DMIBAR registers
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Dump Intel(R) northbridge DMIBAR registers.
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.TP
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.B "\-P, \-\-pciexbar"
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Dump Intel(R) northbridge PCIEXBAR registers
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Dump Intel(R) northbridge PCIEXBAR registers.
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.TP
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.B "\-M, \-\-msrs"
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Dump Intel(R) CPU MSRs
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Dump Intel(R) CPU MSRs.
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.SH BUGS
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Please report any bugs at
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.BR http://tracker.coreboot.org/trac/coreboot/newticket ","
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@ -54,13 +55,13 @@ or on the coreboot mailing list
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.B inteltool
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is covered by the GNU General Public License (GPL), version 2.
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.SH COPYRIGHT
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(C) 2008 coresystems GmbH
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Copyright (C) 2008 coresystems GmbH
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.SH AUTHORS
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Stefan Reinauer <stepan@coresystems.de>
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.PP
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This manual page was written by Stefan Reinauer <stepan@coresystems.de>.
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It is licensed under the terms of the GNU GPL (version 2).
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Intel(R) is a registered trademark of Intel Corporation. Other product and/or company names mentioned herein may be trademarks or registered trademarks of their respective owners.
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.sp
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Intel(R) is a registered trademark of Intel Corporation. Other product
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and/or company names mentioned herein may be trademarks or registered
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trademarks of their respective owners.
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@ -32,7 +32,7 @@
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#define INTELTOOL_VERSION "1.0"
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/* Tested Chipsets: */
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/* Tested chipsets: */
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#define PCI_VENDOR_ID_INTEL 0x8086
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#define PCI_DEVICE_ID_INTEL_ICH 0x2410
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#define PCI_DEVICE_ID_INTEL_ICH0 0x2420
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@ -59,9 +59,6 @@ static const struct {
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH, "ICH" }
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};
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#define ARRAY_SIZE(a) ((int)(sizeof(a) / sizeof((a)[0])))
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int fd_mem;
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@ -70,7 +67,6 @@ int fd_msr;
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typedef struct { uint32_t hi, lo; } msr_t;
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typedef struct { uint16_t addr; int size; char *name; } io_register_t;
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static const io_register_t ich0_gpio_registers[] = {
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{ 0x00, 4, "GPIO_USE_SEL" },
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{ 0x04, 4, "GP_IO_SEL" },
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@ -272,7 +268,6 @@ int print_pmbase(struct pci_dev *sb)
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/*
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* (G)MCH MMIO Config Space
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*/
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int print_mchbar(struct pci_dev *nb)
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{
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int i, size = (16 * 1024);
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@ -317,7 +312,7 @@ int print_mchbar(struct pci_dev *nb)
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*/
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int print_epbar(struct pci_dev *nb)
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{
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int i, size=4096;
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int i, size = (4 * 1024);
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volatile uint8_t *epbar;
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uint32_t epbar_phys;
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@ -353,13 +348,12 @@ int print_epbar(struct pci_dev *nb)
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return 0;
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}
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/*
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* MCH-ICH Serial Interconnect Ingress Root Complex MMIO configuration space
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*/
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int print_dmibar(struct pci_dev *nb)
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{
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int i, size=4096;
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int i, size = (4 * 1024);
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volatile uint8_t *dmibar;
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uint32_t dmibar_phys;
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@ -439,14 +433,14 @@ int print_pciexbar(struct pci_dev *nb)
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max_busses = 64;
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break;
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default: // RSVD
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printf("Undefined Address base. Bailing out\n");
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printf("Undefined address base. Bailing out.\n");
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return 1;
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}
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printf("PCIEXBAR: 0x%08x\n", pciexbar_phys);
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pciexbar = mmap(0, (max_busses * 1024 * 1024), PROT_WRITE | PROT_READ, MAP_SHARED,
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fd_mem, (off_t) pciexbar_phys );
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pciexbar = mmap(0, (max_busses * 1024 * 1024), PROT_WRITE | PROT_READ,
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MAP_SHARED, fd_mem, (off_t) pciexbar_phys);
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if (pciexbar == MAP_FAILED) {
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perror("Error mapping PCIEXBAR");
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@ -490,7 +484,7 @@ int msr_readerror = 0;
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msr_t rdmsr(int addr)
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{
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unsigned char buf[8];
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uint8_t buf[8];
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msr_t msr = { 0xffffffff, 0xffffffff };
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if (lseek(fd_msr, (off_t) addr, SEEK_SET) == -1) {
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@ -524,7 +518,6 @@ int print_intel_core_msrs(void)
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unsigned int i, core;
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msr_t msr;
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#define IA32_PLATFORM_ID 0x0017
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#define EBL_CR_POWERON 0x002a
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#define FSB_CLK_STS 0x00cd
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@ -622,10 +615,10 @@ int print_intel_core_msrs(void)
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for (i = 0; i < ARRAY_SIZE(global_msrs); i++) {
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msr = rdmsr(global_msrs[i].number);
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printf(" MSR 0x%08X = 0x%08X:0x%08X (%s)\n",
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global_msrs[i].number, msr.hi, msr.lo, global_msrs[i].name);
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global_msrs[i].number, msr.hi, msr.lo,
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global_msrs[i].name);
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}
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close(fd_msr);
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for (core = 0; core < 8; core++) {
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@ -634,19 +627,20 @@ int print_intel_core_msrs(void)
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sprintf(msrfilename, "/dev/cpu/%d/msr", core);
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fd_msr = open(msrfilename, O_RDWR);
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if (fd_msr<0) {
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/* If the file is not there, we're probably through.
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* No error, since we successfully opened /dev/cpu/0/msr before
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/* If the file is not there, we're probably through. No error,
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* since we successfully opened /dev/cpu/0/msr before.
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*/
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if (fd_msr < 0)
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break;
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}
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printf("\n====================== UNIQUE MSRs (core %d) ======================\n", core);
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for (i = 0; i < ARRAY_SIZE(per_core_msrs); i++) {
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msr = rdmsr(per_core_msrs[i].number);
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printf(" MSR 0x%08X = 0x%08X:0x%08X (%s)\n",
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per_core_msrs[i].number, msr.hi, msr.lo, per_core_msrs[i].name);
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per_core_msrs[i].number, msr.hi, msr.lo,
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per_core_msrs[i].name);
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}
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close(fd_msr);
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@ -697,9 +691,7 @@ int main(int argc, char *argv[])
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{
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struct pci_access *pacc;
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struct pci_dev *sb, *nb;
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int opt;
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int option_index = 0;
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int i;
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int i, opt, option_index = 0;
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char *sbname = "unknown", *nbname = "unknown";
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@ -772,7 +764,10 @@ int main(int argc, char *argv[])
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}
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}
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if (iopl(3)) { printf("You need to be root.\n"); exit(1); }
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if (iopl(3)) {
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printf("You need to be root.\n");
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exit(1);
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}
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if ((fd_mem = open("/dev/mem", O_RDWR)) < 0) {
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perror("Can not open /dev/mem");
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@ -783,7 +778,6 @@ int main(int argc, char *argv[])
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pci_init(pacc);
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pci_scan_bus(pacc);
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/* Find the required devices */
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sb = pci_get_dev(pacc, 0, 0, 0x1f, 0);
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@ -870,9 +864,7 @@ int main(int argc, char *argv[])
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printf("\n\n");
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}
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/* Clean up */
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pci_free_dev(nb);
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pci_free_dev(sb);
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pci_cleanup(pacc);
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