Cosmetics, whitespace, coding style, partially ident-aided (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3318 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann
parent
621c09563b
commit
9a6b6b51df
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@ -39,7 +39,7 @@ clean:
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distclean: clean
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rm -f $(PROGRAM) .dependencies
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dep:
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@$(CC) -MM *.c > .dependencies
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@ -1,4 +1,4 @@
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.TH INTELTOOL 8 "May 12, 2008"
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.TH INTELTOOL 8 "May 14, 2008"
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.SH NAME
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inteltool \- a tool for dumping Intel(R) CPU / chipset configuration parameters
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.SH SYNOPSIS
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@ -7,9 +7,9 @@ inteltool \- a tool for dumping Intel(R) CPU / chipset configuration parameters
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.B inteltool
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is a handy little tool for dumping the configuration space of Intel(R)
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CPUs, northbridges and southbridges.
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.sp
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This tool has been developed for the coreboot project (see
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.B http://www.coreboot.org/
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.B http://coreboot.org
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for details on coreboot).
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.SH OPTIONS
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.TP
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@ -20,31 +20,32 @@ Show a help text and exit.
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Show version information and exit.
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.TP
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.B "\-a, \-\-all"
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Dump all known I/O Controller Hub (ICH) southbridge, Intel(R) northbridge and Intel(R) Core CPU MSRs.
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Dump all known I/O Controller Hub (ICH) southbridge, Intel(R) northbridge
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and Intel(R) Core CPU MSRs.
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.TP
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.B "\-g, \-\-gpio"
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Dump I/O Controller Hub (ICH) southbridge GPIO registers
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Dump I/O Controller Hub (ICH) southbridge GPIO registers.
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.TP
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.B "\-r, \-\-rcba"
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Dump I/O Controller Hub (ICH) southbridge RCBA registers
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Dump I/O Controller Hub (ICH) southbridge RCBA registers.
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.TP
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.B "\-p, \-\-pmbase"
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Dump I/O Controller Hub (ICH) southbridge pmbase registers
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Dump I/O Controller Hub (ICH) southbridge PMBASE registers.
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.TP
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.B "\-m, \-\-mchbar"
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Dump Intel(R) northbridge MCHBAR registers
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Dump Intel(R) northbridge MCHBAR registers.
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.TP
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.B "\-e, \-\-epbar"
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Dump Intel(R) northbridge EPBAR registers
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Dump Intel(R) northbridge EPBAR registers.
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.TP
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.B "\-d, \-\-dmibar"
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Dump Intel(R) northbridge DMIBAR registers
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Dump Intel(R) northbridge DMIBAR registers.
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.TP
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.B "\-P, \-\-pciexbar"
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Dump Intel(R) northbridge PCIEXBAR registers
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Dump Intel(R) northbridge PCIEXBAR registers.
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.TP
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.B "\-M, \-\-msrs"
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Dump Intel(R) CPU MSRs
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Dump Intel(R) CPU MSRs.
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.SH BUGS
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Please report any bugs at
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.BR http://tracker.coreboot.org/trac/coreboot/newticket ","
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@ -54,13 +55,13 @@ or on the coreboot mailing list
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.B inteltool
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is covered by the GNU General Public License (GPL), version 2.
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.SH COPYRIGHT
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(C) 2008 coresystems GmbH
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Copyright (C) 2008 coresystems GmbH
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.SH AUTHORS
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Stefan Reinauer <stepan@coresystems.de>
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.PP
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This manual page was written by Stefan Reinauer <stepan@coresystems.de>.
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It is licensed under the terms of the GNU GPL (version 2).
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Intel(R) is a registered trademark of Intel Corporation. Other product and/or company names mentioned herein may be trademarks or registered trademarks of their respective owners.
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.sp
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Intel(R) is a registered trademark of Intel Corporation. Other product
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and/or company names mentioned herein may be trademarks or registered
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trademarks of their respective owners.
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@ -32,7 +32,7 @@
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#define INTELTOOL_VERSION "1.0"
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/* Tested Chipsets: */
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/* Tested chipsets: */
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#define PCI_VENDOR_ID_INTEL 0x8086
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#define PCI_DEVICE_ID_INTEL_ICH 0x2410
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#define PCI_DEVICE_ID_INTEL_ICH0 0x2420
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@ -46,7 +46,7 @@
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static const struct {
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uint16_t vendor_id, device_id;
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char * name;
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char *name;
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} supported_chips_list[] = {
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GM, "i945GM" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7MDH, "ICH7-M DH" },
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@ -59,9 +59,6 @@ static const struct {
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH, "ICH" }
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};
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#define ARRAY_SIZE(a) ((int)(sizeof(a) / sizeof((a)[0])))
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int fd_mem;
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@ -70,8 +67,7 @@ int fd_msr;
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typedef struct { uint32_t hi, lo; } msr_t;
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typedef struct { uint16_t addr; int size; char *name; } io_register_t;
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static const io_register_t ich0_gpio_registers[] = {
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static const io_register_t ich0_gpio_registers[] = {
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{ 0x00, 4, "GPIO_USE_SEL" },
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{ 0x04, 4, "GP_IO_SEL" },
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{ 0x08, 4, "RESERVED" },
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@ -90,7 +86,7 @@ static const io_register_t ich0_gpio_registers[] = {
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{ 0x3C, 4, "RESERVED" }
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};
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static const io_register_t ich4_gpio_registers[] = {
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static const io_register_t ich4_gpio_registers[] = {
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{ 0x00, 4, "GPIO_USE_SEL" },
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{ 0x04, 4, "GP_IO_SEL" },
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{ 0x08, 4, "RESERVED" },
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@ -109,7 +105,7 @@ static const io_register_t ich4_gpio_registers[] = {
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{ 0x3C, 4, "RESERVED" }
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};
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static const io_register_t ich7_gpio_registers[] = {
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static const io_register_t ich7_gpio_registers[] = {
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{ 0x00, 4, "GPIO_USE_SEL" },
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{ 0x04, 4, "GP_IO_SEL" },
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{ 0x08, 4, "RESERVED" },
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@ -167,22 +163,22 @@ int print_gpios(struct pci_dev *sb)
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printf("GPIOBASE = 0x%04x (IO)\n\n", gpiobase);
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for (i=0; i<size; i++) {
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for (i = 0; i < size; i++) {
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switch (gpio_registers[i].size) {
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case 4:
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printf("gpiobase+0x%04x: 0x%08x (%s)\n",
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printf("gpiobase+0x%04x: 0x%08x (%s)\n",
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gpio_registers[i].addr,
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inl(gpiobase+gpio_registers[i].addr),
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gpio_registers[i].name);
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break;
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case 2:
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printf("gpiobase+0x%04x: 0x%04x (%s)\n",
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printf("gpiobase+0x%04x: 0x%04x (%s)\n",
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gpio_registers[i].addr,
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inw(gpiobase+gpio_registers[i].addr),
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gpio_registers[i].name);
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break;
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case 1:
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printf("gpiobase+0x%04x: 0x%02x (%s)\n",
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printf("gpiobase+0x%04x: 0x%02x (%s)\n",
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gpio_registers[i].addr,
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inb(gpiobase+gpio_registers[i].addr),
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gpio_registers[i].name);
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@ -195,7 +191,7 @@ int print_gpios(struct pci_dev *sb)
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int print_rcba(struct pci_dev *sb)
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{
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int i, size=0x4000;
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int i, size = 0x4000;
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volatile uint8_t *rcba;
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uint32_t rcba_phys;
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@ -206,7 +202,7 @@ int print_rcba(struct pci_dev *sb)
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case PCI_DEVICE_ID_INTEL_ICH7M:
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case PCI_DEVICE_ID_INTEL_ICH7DH:
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case PCI_DEVICE_ID_INTEL_ICH7MDH:
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rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe;
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rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe;
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break;
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case PCI_DEVICE_ID_INTEL_ICH:
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case PCI_DEVICE_ID_INTEL_ICH0:
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@ -229,18 +225,18 @@ int print_rcba(struct pci_dev *sb)
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printf("RCBA = 0x%08x (MEM)\n\n", rcba_phys);
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for (i=0; i<size; i+=4) {
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if(*(uint32_t *)(rcba+i))
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printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(rcba+i));
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for (i = 0; i < size; i += 4) {
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if (*(uint32_t *)(rcba + i))
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printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(rcba + i));
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}
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munmap((void *) rcba, size);
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munmap((void *)rcba, size);
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return 0;
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}
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int print_pmbase(struct pci_dev *sb)
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{
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int i, size=0x80;
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int i, size = 0x80;
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uint16_t pmbase;
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printf("\n============= PMBASE ============\n\n");
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@ -250,7 +246,7 @@ int print_pmbase(struct pci_dev *sb)
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case PCI_DEVICE_ID_INTEL_ICH7M:
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case PCI_DEVICE_ID_INTEL_ICH7DH:
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case PCI_DEVICE_ID_INTEL_ICH7MDH:
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pmbase = pci_read_word(sb, 0x40) & 0xfffc;
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pmbase = pci_read_word(sb, 0x40) & 0xfffc;
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break;
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case 0x1234: // Dummy for non-existent functionality
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printf("This southbridge does not have PMBASE.\n");
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printf("PMBASE = 0x%04x (IO)\n\n", pmbase);
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for (i=0; i<size; i+=4) {
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printf("pmbase+0x%04x: 0x%08x\n", i, inl(pmbase+i));
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for (i = 0; i < size; i += 4) {
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printf("pmbase+0x%04x: 0x%08x\n", i, inl(pmbase + i));
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}
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return 0;
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@ -272,10 +268,9 @@ int print_pmbase(struct pci_dev *sb)
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/*
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* (G)MCH MMIO Config Space
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*/
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int print_mchbar(struct pci_dev *nb)
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{
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int i, size=(16*1024);
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int i, size = (16 * 1024);
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volatile uint8_t *mchbar;
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uint32_t mchbar_phys;
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@ -283,7 +278,7 @@ int print_mchbar(struct pci_dev *nb)
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switch (nb->device_id) {
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case PCI_DEVICE_ID_INTEL_82945GM:
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mchbar_phys = pci_read_long(nb, 0x44) & 0xfffffffe;
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mchbar_phys = pci_read_long(nb, 0x44) & 0xfffffffe;
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break;
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case 0x1234: // Dummy for non-existent functionality
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printf("This northbrigde does not have MCHBAR.\n");
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@ -294,7 +289,7 @@ int print_mchbar(struct pci_dev *nb)
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}
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mchbar = mmap(0, size, PROT_WRITE | PROT_READ, MAP_SHARED,
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fd_mem, (off_t) mchbar_phys );
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fd_mem, (off_t) mchbar_phys);
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if (mchbar == MAP_FAILED) {
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perror("Error mapping MCHBAR");
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@ -303,12 +298,12 @@ int print_mchbar(struct pci_dev *nb)
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printf("MCHBAR = 0x%08x (MEM)\n\n", mchbar_phys);
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for (i=0; i<size; i+=4) {
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if(*(uint32_t *)(mchbar+i))
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for (i = 0; i < size; i += 4) {
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if (*(uint32_t *)(mchbar + i))
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printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(mchbar+i));
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}
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munmap((void *) mchbar, size);
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munmap((void *)mchbar, size);
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return 0;
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}
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@ -317,7 +312,7 @@ int print_mchbar(struct pci_dev *nb)
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*/
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int print_epbar(struct pci_dev *nb)
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{
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int i, size=4096;
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int i, size = (4 * 1024);
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volatile uint8_t *epbar;
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uint32_t epbar_phys;
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@ -325,7 +320,7 @@ int print_epbar(struct pci_dev *nb)
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switch (nb->device_id) {
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case PCI_DEVICE_ID_INTEL_82945GM:
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epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe;
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epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe;
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break;
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case 0x1234: // Dummy for non-existent functionality
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printf("This northbrigde does not have EPBAR.\n");
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@ -336,7 +331,7 @@ int print_epbar(struct pci_dev *nb)
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}
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epbar = mmap(0, size, PROT_WRITE | PROT_READ, MAP_SHARED,
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fd_mem, (off_t) epbar_phys );
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fd_mem, (off_t) epbar_phys);
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if (epbar == MAP_FAILED) {
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perror("Error mapping EPBAR");
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@ -344,22 +339,21 @@ int print_epbar(struct pci_dev *nb)
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}
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printf("EPBAR = 0x%08x (MEM)\n\n", epbar_phys);
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for (i=0; i<size; i+=4) {
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if(*(uint32_t *)(epbar+i))
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for (i = 0; i < size; i += 4) {
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if (*(uint32_t *)(epbar + i))
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printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(epbar+i));
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}
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munmap((void *) epbar, size);
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munmap((void *)epbar, size);
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return 0;
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}
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/*
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* MCH-ICH Serial Interconnect Ingress Root Complex MMIO configuration space
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* MCH-ICH Serial Interconnect Ingress Root Complex MMIO configuration space
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*/
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int print_dmibar(struct pci_dev *nb)
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{
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int i, size=4096;
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int i, size = (4 * 1024);
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volatile uint8_t *dmibar;
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uint32_t dmibar_phys;
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@ -367,7 +361,7 @@ int print_dmibar(struct pci_dev *nb)
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|
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switch (nb->device_id) {
|
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case PCI_DEVICE_ID_INTEL_82945GM:
|
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dmibar_phys = pci_read_long(nb, 0x4c) & 0xfffffffe;
|
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dmibar_phys = pci_read_long(nb, 0x4c) & 0xfffffffe;
|
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break;
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case 0x1234: // Dummy for non-existent functionality
|
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printf("This northbrigde does not have DMIBAR.\n");
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|
|
@ -378,7 +372,7 @@ int print_dmibar(struct pci_dev *nb)
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}
|
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|
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dmibar = mmap(0, size, PROT_WRITE | PROT_READ, MAP_SHARED,
|
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fd_mem, (off_t) dmibar_phys );
|
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fd_mem, (off_t) dmibar_phys);
|
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|
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if (dmibar == MAP_FAILED) {
|
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perror("Error mapping DMIBAR");
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|
|
@ -386,12 +380,12 @@ int print_dmibar(struct pci_dev *nb)
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}
|
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|
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printf("DMIBAR = 0x%08x (MEM)\n\n", dmibar_phys);
|
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for (i=0; i<size; i+=4) {
|
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if(*(uint32_t *)(dmibar+i))
|
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for (i = 0; i < size; i += 4) {
|
||||
if (*(uint32_t *)(dmibar + i))
|
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printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(dmibar+i));
|
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}
|
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|
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munmap((void *) dmibar, size);
|
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munmap((void *)dmibar, size);
|
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return 0;
|
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}
|
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|
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|
|
@ -410,7 +404,7 @@ int print_pciexbar(struct pci_dev *nb)
|
|||
|
||||
switch (nb->device_id) {
|
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case PCI_DEVICE_ID_INTEL_82945GM:
|
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pciexbar_reg = pci_read_long(nb, 0x48);
|
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pciexbar_reg = pci_read_long(nb, 0x48);
|
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break;
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case 0x1234: // Dummy for non-existent functionality
|
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printf("Error: This northbrigde does not have PCIEXBAR.\n");
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|
@ -420,7 +414,7 @@ int print_pciexbar(struct pci_dev *nb)
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return 1;
|
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}
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|
||||
if( !(pciexbar_reg & (1 << 0))) {
|
||||
if (!(pciexbar_reg & (1 << 0))) {
|
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printf("PCIEXBAR register is disabled.\n");
|
||||
return 0;
|
||||
}
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||||
|
|
@ -439,14 +433,14 @@ int print_pciexbar(struct pci_dev *nb)
|
|||
max_busses = 64;
|
||||
break;
|
||||
default: // RSVD
|
||||
printf("Undefined Address base. Bailing out\n");
|
||||
printf("Undefined address base. Bailing out.\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
printf("PCIEXBAR: 0x%08x\n", pciexbar_phys);
|
||||
|
||||
pciexbar = mmap(0, (max_busses * 1024 * 1024), PROT_WRITE | PROT_READ, MAP_SHARED,
|
||||
fd_mem, (off_t) pciexbar_phys );
|
||||
pciexbar = mmap(0, (max_busses * 1024 * 1024), PROT_WRITE | PROT_READ,
|
||||
MAP_SHARED, fd_mem, (off_t) pciexbar_phys);
|
||||
|
||||
if (pciexbar == MAP_FAILED) {
|
||||
perror("Error mapping PCIEXBAR");
|
||||
|
|
@ -471,7 +465,7 @@ int print_pciexbar(struct pci_dev *nb)
|
|||
}
|
||||
|
||||
printf("\nPCIe %02x:%02x.%01x extended config space:", bus, dev, fn);
|
||||
for (i=0; i<4096; i++) {
|
||||
for (i = 0; i < 4096; i++) {
|
||||
if((i % 0x10) == 0)
|
||||
printf("\n%04x:", i);
|
||||
printf(" %02x", *(pciexbar+devbase+i));
|
||||
|
|
@ -481,7 +475,7 @@ int print_pciexbar(struct pci_dev *nb)
|
|||
}
|
||||
}
|
||||
|
||||
munmap((void *) pciexbar, (max_busses * 1024 * 1024));
|
||||
munmap((void *)pciexbar, (max_busses * 1024 * 1024));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -490,7 +484,7 @@ int msr_readerror = 0;
|
|||
|
||||
msr_t rdmsr(int addr)
|
||||
{
|
||||
unsigned char buf[8];
|
||||
uint8_t buf[8];
|
||||
msr_t msr = { 0xffffffff, 0xffffffff };
|
||||
|
||||
if (lseek(fd_msr, (off_t) addr, SEEK_SET) == -1) {
|
||||
|
|
@ -501,7 +495,7 @@ msr_t rdmsr(int addr)
|
|||
|
||||
if (read(fd_msr, buf, 8) == 8) {
|
||||
msr.lo = *(uint32_t *)buf;
|
||||
msr.hi = *(uint32_t *)(buf+4);
|
||||
msr.hi = *(uint32_t *)(buf + 4);
|
||||
|
||||
return msr;
|
||||
}
|
||||
|
|
@ -524,7 +518,6 @@ int print_intel_core_msrs(void)
|
|||
unsigned int i, core;
|
||||
msr_t msr;
|
||||
|
||||
|
||||
#define IA32_PLATFORM_ID 0x0017
|
||||
#define EBL_CR_POWERON 0x002a
|
||||
#define FSB_CLK_STS 0x00cd
|
||||
|
|
@ -610,8 +603,8 @@ int print_intel_core_msrs(void)
|
|||
//{ 0x00c000080, "IA32_CR_EFER" }, // Seems to be RO
|
||||
};
|
||||
|
||||
fd_msr = open("/dev/cpu/0/msr", O_RDWR);
|
||||
if (fd_msr<0) {
|
||||
fd_msr = open("/dev/cpu/0/msr", O_RDWR);
|
||||
if (fd_msr < 0) {
|
||||
perror("Error while opening /dev/cpu/0/msr");
|
||||
printf("Did you run 'modprobe msr'?\n");
|
||||
return -1;
|
||||
|
|
@ -622,38 +615,39 @@ int print_intel_core_msrs(void)
|
|||
for (i = 0; i < ARRAY_SIZE(global_msrs); i++) {
|
||||
msr = rdmsr(global_msrs[i].number);
|
||||
printf(" MSR 0x%08X = 0x%08X:0x%08X (%s)\n",
|
||||
global_msrs[i].number, msr.hi, msr.lo, global_msrs[i].name);
|
||||
global_msrs[i].number, msr.hi, msr.lo,
|
||||
global_msrs[i].name);
|
||||
}
|
||||
|
||||
|
||||
close(fd_msr);
|
||||
|
||||
for (core=0; core < 8; core++) {
|
||||
|
||||
for (core = 0; core < 8; core++) {
|
||||
char msrfilename[64];
|
||||
memset(msrfilename, 0, 64);
|
||||
sprintf(msrfilename, "/dev/cpu/%d/msr", core);
|
||||
|
||||
fd_msr = open(msrfilename, O_RDWR);
|
||||
if (fd_msr<0) {
|
||||
/* If the file is not there, we're probably through.
|
||||
* No error, since we successfully opened /dev/cpu/0/msr before
|
||||
*/
|
||||
|
||||
/* If the file is not there, we're probably through. No error,
|
||||
* since we successfully opened /dev/cpu/0/msr before.
|
||||
*/
|
||||
if (fd_msr < 0)
|
||||
break;
|
||||
}
|
||||
|
||||
printf("\n====================== UNIQUE MSRs (core %d) ======================\n", core);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(per_core_msrs); i++) {
|
||||
msr = rdmsr(per_core_msrs[i].number);
|
||||
printf(" MSR 0x%08X = 0x%08X:0x%08X (%s)\n",
|
||||
per_core_msrs[i].number, msr.hi, msr.lo, per_core_msrs[i].name);
|
||||
per_core_msrs[i].number, msr.hi, msr.lo,
|
||||
per_core_msrs[i].name);
|
||||
}
|
||||
|
||||
close(fd_msr);
|
||||
}
|
||||
|
||||
if (msr_readerror)
|
||||
printf("\n(*) Some MSRs could not be read. The marked values are unreliable.\n");
|
||||
printf("\n(*) Some MSRs could not be read. The marked values are unreliable.\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -689,7 +683,7 @@ void print_usage(const char *name)
|
|||
" -P | --pciexpress: dump northbridge PCIEXBAR registers\n\n"
|
||||
" -M | --msrs: dump CPU MSRs\n"
|
||||
" -a | --all: dump all known registers\n"
|
||||
"\n");
|
||||
"\n");
|
||||
exit(1);
|
||||
}
|
||||
|
||||
|
|
@ -697,15 +691,13 @@ int main(int argc, char *argv[])
|
|||
{
|
||||
struct pci_access *pacc;
|
||||
struct pci_dev *sb, *nb;
|
||||
int opt;
|
||||
int option_index = 0;
|
||||
int i;
|
||||
int i, opt, option_index = 0;
|
||||
|
||||
char *sbname="unknown", *nbname="unknown";
|
||||
char *sbname = "unknown", *nbname = "unknown";
|
||||
|
||||
int dump_gpios=0, dump_mchbar=0, dump_rcba=0;
|
||||
int dump_pmbase=0, dump_epbar=0, dump_dmibar=0;
|
||||
int dump_pciexbar=0, dump_coremsrs=0;
|
||||
int dump_gpios = 0, dump_mchbar = 0, dump_rcba = 0;
|
||||
int dump_pmbase = 0, dump_epbar = 0, dump_dmibar = 0;
|
||||
int dump_pciexbar = 0, dump_coremsrs = 0;
|
||||
|
||||
static struct option long_options[] = {
|
||||
{"version", 0, 0, 'v'},
|
||||
|
|
@ -723,7 +715,7 @@ int main(int argc, char *argv[])
|
|||
};
|
||||
|
||||
while ((opt = getopt_long(argc, argv, "vh?grpmedPMa",
|
||||
long_options, &option_index)) != EOF) {
|
||||
long_options, &option_index)) != EOF) {
|
||||
switch (opt) {
|
||||
case 'v':
|
||||
print_version();
|
||||
|
|
@ -772,7 +764,10 @@ int main(int argc, char *argv[])
|
|||
}
|
||||
}
|
||||
|
||||
if (iopl(3)) { printf("You need to be root.\n"); exit(1); }
|
||||
if (iopl(3)) {
|
||||
printf("You need to be root.\n");
|
||||
exit(1);
|
||||
}
|
||||
|
||||
if ((fd_mem = open("/dev/mem", O_RDWR)) < 0) {
|
||||
perror("Can not open /dev/mem");
|
||||
|
|
@ -783,7 +778,6 @@ int main(int argc, char *argv[])
|
|||
pci_init(pacc);
|
||||
pci_scan_bus(pacc);
|
||||
|
||||
|
||||
/* Find the required devices */
|
||||
|
||||
sb = pci_get_dev(pacc, 0, 0, 0x1f, 0);
|
||||
|
|
@ -815,10 +809,10 @@ int main(int argc, char *argv[])
|
|||
/* TODO check cpuid, too */
|
||||
|
||||
/* Determine names */
|
||||
for (i=0; i<ARRAY_SIZE(supported_chips_list); i++)
|
||||
for (i = 0; i < ARRAY_SIZE(supported_chips_list); i++)
|
||||
if (nb->device_id == supported_chips_list[i].device_id)
|
||||
nbname = supported_chips_list[i].name;
|
||||
for (i=0; i<ARRAY_SIZE(supported_chips_list); i++)
|
||||
for (i = 0; i < ARRAY_SIZE(supported_chips_list); i++)
|
||||
if (sb->device_id == supported_chips_list[i].device_id)
|
||||
sbname = supported_chips_list[i].name;
|
||||
|
||||
|
|
@ -870,9 +864,7 @@ int main(int argc, char *argv[])
|
|||
printf("\n\n");
|
||||
}
|
||||
|
||||
|
||||
/* Clean up */
|
||||
|
||||
pci_free_dev(nb);
|
||||
pci_free_dev(sb);
|
||||
pci_cleanup(pacc);
|
||||
|
|
|
|||
Loading…
Reference in New Issue