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soc/amd/cezanne: select common APOB NV cache code 

BUG=b:181766974

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I660f19d18810c35dafcd75bcd1993216b7b09644
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51268
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Held 2021-03-05 00:14:08 +01:00
parent e1a27f2e49
commit 9a6bc07cc2
2 changed files with 5 additions and 0 deletions
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1
src/soc/amd/cezanne/Kconfig
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@ -31,6 +31,7 @@ config SOC_SPECIFIC_OPTIONS
select SOC_AMD_COMMON_BLOCK_ACPI
select SOC_AMD_COMMON_BLOCK_ACPIMMIO
select SOC_AMD_COMMON_BLOCK_AOAC
select SOC_AMD_COMMON_BLOCK_APOB
select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS
select SOC_AMD_COMMON_BLOCK_DATA_FABRIC
select SOC_AMD_COMMON_BLOCK_HAS_ESPI

4
src/soc/amd/cezanne/romstage.c
View File

@ -2,6 +2,7 @@
#include <acpi/acpi.h>
#include <amdblocks/acpimmio.h>
#include <amdblocks/apob_cache.h>
#include <amdblocks/memmap.h>
#include <arch/cpu.h>
#include <console/console.h>
@ -13,6 +14,8 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
{
FSP_M_CONFIG *mcfg = &mupd->FspmConfig;
mupd->FspmArchUpd.NvsBufferPtr = (uintptr_t)soc_fill_apob_cache();
mcfg->pci_express_base_addr = CONFIG_MMCONF_BASE_ADDRESS;
mcfg->tseg_size = CONFIG_SMM_TSEG_SIZE;
mcfg->bert_size = CONFIG_ACPI_BERT_SIZE;
@ -31,6 +34,7 @@ asmlinkage void car_stage_entry(void)
post_code(0x41);
fsp_memory_init(acpi_is_wakeup_s3());
soc_update_apob_cache();
/* Fixup settings FSP-M should not be changing */
fch_disable_legacy_dma_io();